msm: pcie: correct cached PCIe link BW max gen speed



PCIe link BW (bandwidth) max GEN speed is incorrectly calculated.
Update bw_gen_max to have to the correct value.

Change-Id: I5a9c77e326966681bdc0efde84815dcea083d470
Signed-off-by: Tony Truong <truong@codeaurora.org>

parent af0ad3b9

drivers/pci/host/pci-msm.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -3724,7 +3724,7 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev,
		of_property_read_u32_array(pdev->dev.of_node, "qcom,bw-scale",
		(u32 *)dev->bw_scale, size / sizeof(u32));

		dev->bw_gen_max = size / sizeof(u32);
		dev->bw_gen_max = size / sizeof(*dev->bw_scale);
		} else {
		PCIE_DBG(dev, "RC%d: bandwidth scaling is not supported\n",
		dev->rc_idx);