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Commit c26ff4cb authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: ep_pcie: Update bit to read if the PHY is ready"

parents a03cd4f9 bcec534d

Documentation/devicetree/bindings/pci/msm_ep_pcie.txt

+2 −0
Original line number Diff line number Diff line
@@ -48,6 +48,8 @@ Optional Properties: 
  - qcom,phy-init: The initialization sequence to bring up the PCIe PHY.

    Should be specified in groups (offset, value, delay, direction).

  - qcom,phy-status-reg: Register offset for PHY status.

  - qcom,phy-status-reg2: For sdxprairie and above use only

    qcom,phy-status-reg2 as register offset for PHY status.

  - qcom,dbi-base-reg: Register offset for DBI base address.

  - qcom,slv-space-reg: Register offset for slave address space size.

  - qcom,pcie-vendor-id: Vendor id to be written to the Vendor ID register.

drivers/platform/msm/ep_pcie/ep_pcie_com.h

+1 −0
Original line number Diff line number Diff line
@@ -372,6 +372,7 @@ struct ep_pcie_dev_t { 
	u32                          dbi_base_reg;

	u32                          slv_space_reg;

	u32                          phy_status_reg;

	u32			phy_status_bit_mask_bit;

	u32                          phy_init_len;

	u32			     mhi_soc_reset_offset;

	struct ep_pcie_phy_info_t    *phy_init;

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+15 −0
Original line number Diff line number Diff line
@@ -3083,6 +3083,21 @@ static int ep_pcie_probe(struct platform_device *pdev) 
		EP_PCIE_DBG(&ep_pcie_dev, "PCIe V%d: phy-status-reg:0x%x\n",

			ep_pcie_dev.rev, ep_pcie_dev.phy_status_reg);



	ep_pcie_dev.phy_status_bit_mask_bit = BIT(6);



	ret = of_property_read_u32((&pdev->dev)->of_node,

				"qcom,phy-status-reg2",

				&ep_pcie_dev.phy_status_reg);

	if (ret) {

		EP_PCIE_DBG(&ep_pcie_dev,

			"PCIe V%d: phy-status-reg2 does not exist\n",

			ep_pcie_dev.rev);

	} else {

		EP_PCIE_DBG(&ep_pcie_dev, "PCIe V%d: phy-status-reg2:0x%x\n",

			ep_pcie_dev.rev, ep_pcie_dev.phy_status_reg);

		ep_pcie_dev.phy_status_bit_mask_bit = BIT(7);

	}



	ep_pcie_dev.phy_rev = 1;

	ret = of_property_read_u32((&pdev->dev)->of_node,

				"qcom,pcie-phy-ver",

drivers/platform/msm/ep_pcie/ep_pcie_phy.c

+2 −2
Original line number Diff line number Diff line 
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2015-2018, 2019-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -158,7 +158,7 @@ bool ep_pcie_phy_is_ready(struct ep_pcie_dev_t *dev) 
	else

		offset = PCIE_PHY_PCS_STATUS;



	if (readl_relaxed(dev->phy + offset) & BIT(6))

	if (readl_relaxed(dev->phy + offset) & dev->phy_status_bit_mask_bit)

		return false;

	else

		return true;