clk: qcom: mdss: modify the DP link clock divider to 10

Change the DP link clock divider to 10 and update the programming
sequence for the divider for 14nm Display Port PLL driver as per
the latest h/w programming guide.

Change-Id: Ibcea4cfc758578c1592438bbdf7ac0400c008621
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
Signed-off-by: Abhijith Desai <desaia@codeaurora.org>