Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c109bf95 authored by Borislav Petkov's avatar Borislav Petkov Committed by Ingo Molnar
Browse files

x86/cpufeature: Remove cpu_has_pge 



Use static_cpu_has() in __flush_tlb_all() due to the time-sensitivity of
this one.

Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1459266123-21878-10-git-send-email-bp@alien8.de


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 054efb64

arch/x86/include/asm/cpufeature.h

+0 −1
Original line number Diff line number Diff line
@@ -121,7 +121,6 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; 
#define cpu_has_fpu		boot_cpu_has(X86_FEATURE_FPU)

#define cpu_has_pse		boot_cpu_has(X86_FEATURE_PSE)

#define cpu_has_tsc		boot_cpu_has(X86_FEATURE_TSC)

#define cpu_has_pge		boot_cpu_has(X86_FEATURE_PGE)

#define cpu_has_apic		boot_cpu_has(X86_FEATURE_APIC)

#define cpu_has_fxsr		boot_cpu_has(X86_FEATURE_FXSR)

#define cpu_has_xmm		boot_cpu_has(X86_FEATURE_XMM)

arch/x86/include/asm/tlbflush.h

+1 −1
Original line number Diff line number Diff line
@@ -181,7 +181,7 @@ static inline void __native_flush_tlb_single(unsigned long addr) 


static inline void __flush_tlb_all(void)

{

	if (cpu_has_pge)

	if (static_cpu_has(X86_FEATURE_PGE))

		__flush_tlb_global();

	else

		__flush_tlb();

arch/x86/kernel/cpu/intel.c

+3 −3
Original line number Diff line number Diff line
@@ -152,9 +152,9 @@ static void early_init_intel(struct cpuinfo_x86 *c) 
	 *  the TLB when any changes are made to any of the page table entries.

	 *  The operating system must reload CR3 to cause the TLB to be flushed"

	 *

	 * As a result cpu_has_pge() in arch/x86/include/asm/tlbflush.h should

	 * be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE

	 * to be modified

	 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h

	 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE

	 * to be modified.

	 */

	if (c->x86 == 5 && c->x86_model == 9) {

		pr_info("Disabling PGE capability bit\n");

arch/x86/kernel/cpu/mtrr/cyrix.c

+2 −2
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ static void prepare_set(void) 
	u32 cr0;



	/*  Save value of CR4 and clear Page Global Enable (bit 7)  */

	if (cpu_has_pge) {

	if (boot_cpu_has(X86_FEATURE_PGE)) {

		cr4 = __read_cr4();

		__write_cr4(cr4 & ~X86_CR4_PGE);

	}
@@ -170,7 +170,7 @@ static void post_set(void) 
	write_cr0(read_cr0() & ~X86_CR0_CD);



	/* Restore value of CR4 */

	if (cpu_has_pge)

	if (boot_cpu_has(X86_FEATURE_PGE))

		__write_cr4(cr4);

}

arch/x86/kernel/cpu/mtrr/generic.c

+2 −2
Original line number Diff line number Diff line
@@ -741,7 +741,7 @@ static void prepare_set(void) __acquires(set_atomicity_lock) 
	wbinvd();



	/* Save value of CR4 and clear Page Global Enable (bit 7) */

	if (cpu_has_pge) {

	if (boot_cpu_has(X86_FEATURE_PGE)) {

		cr4 = __read_cr4();

		__write_cr4(cr4 & ~X86_CR4_PGE);

	}
@@ -771,7 +771,7 @@ static void post_set(void) __releases(set_atomicity_lock) 
	write_cr0(read_cr0() & ~X86_CR0_CD);



	/* Restore value of CR4 */

	if (cpu_has_pge)

	if (boot_cpu_has(X86_FEATURE_PGE))

		__write_cr4(cr4);

	raw_spin_unlock(&set_atomicity_lock);

}