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Commit c09b4c7e authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: qcom: sm6150: Update the PLL settings for all PLL"

parents 4978cc01 94c802e5

drivers/clk/qcom/camcc-sm6150.c

+6 −0
Original line number Diff line number Diff line
@@ -167,6 +167,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = { 
	.vco_mask = 0x3 << 20,

	.aux_output_mask = BIT(1),

	.config_ctl_val = 0x4001055b,

	.test_ctl_hi_val = 0x1,

	.test_ctl_hi_mask = 0x1,

};
@@ -199,6 +200,7 @@ static const struct alpha_pll_config cam_cc_pll1_config = { 
	.vco_mask = 0x3 << 20,

	.aux_output_mask = BIT(1),

	.config_ctl_val = 0x4001055b,

	.test_ctl_hi_val = 0x1,

	.test_ctl_hi_mask = 0x1,

};
@@ -228,7 +230,10 @@ static const struct alpha_pll_config cam_cc_pll2_config = { 
	.vco_mask = 0x3 << 20,

	.early_output_mask = BIT(3),

	.aux2_output_mask = BIT(2),

	.post_div_val = 0x1 << 8,

	.post_div_mask = 0x3 << 8,

	.config_ctl_val = 0x04289,

	.test_ctl_val = 0x08000000,

	.test_ctl_mask = 0x08000000,

};
@@ -270,6 +275,7 @@ static const struct alpha_pll_config cam_cc_pll3_config = { 
	.vco_mask = 0x3 << 20,

	.main_output_mask = BIT(0),

	.config_ctl_val = 0x4001055b,

	.test_ctl_hi_val = 0x1,

	.test_ctl_hi_mask = 0x1,

};

drivers/clk/qcom/dispcc-sm6150.c

+1 −0
Original line number Diff line number Diff line
@@ -135,6 +135,7 @@ static const struct alpha_pll_config disp_cc_pll0_config = { 
	.vco_mask = 0x3 << 20,

	.main_output_mask = BIT(0),

	.config_ctl_val = 0x4001055b,

	.test_ctl_hi_val = 0x1,

	.test_ctl_hi_mask = 0x1,

};

drivers/clk/qcom/gpucc-sm6150.c

+2 −0
Original line number Diff line number Diff line
@@ -105,6 +105,7 @@ static struct pll_vco gpu_cc_pll_vco[] = { 
static const struct alpha_pll_config gpu_pll0_config = {

	.l = 0x35,

	.config_ctl_val = 0x4001055b,

	.test_ctl_hi_val = 0x1,

	.test_ctl_hi_mask = 0x1,

	.alpha_u = 0x20,

	.alpha = 0x00,
@@ -118,6 +119,7 @@ static const struct alpha_pll_config gpu_pll0_config = { 
static const struct alpha_pll_config gpu_pll1_config = {

	.l = 0x30,

	.config_ctl_val = 0x4001055b,

	.test_ctl_hi_val = 0x1,

	.test_ctl_hi_mask = 0x1,

	.alpha_u = 0x70,

	.alpha = 0x00,

drivers/clk/qcom/scc-sm6150.c

+1 −0
Original line number Diff line number Diff line
@@ -85,6 +85,7 @@ static const struct alpha_pll_config scc_pll_config = { 
	.aux_output_mask = BIT(1),

	.aux2_output_mask = BIT(2),

	.config_ctl_val = 0x4001055b,

	.test_ctl_hi_val = 0x1,

	.test_ctl_hi_mask = 0x1,

};

drivers/clk/qcom/videocc-sm6150.c

+1 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ static const struct alpha_pll_config video_pll0_config = { 
	.vco_mask = 0x3 << 20,

	.main_output_mask = BIT(0),

	.config_ctl_val = 0x4001055b,

	.test_ctl_hi_val = 0x1,

	.test_ctl_hi_mask = 0x1,

};