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Commit c00f3188 authored by Niklas Cassel's avatar Niklas Cassel Committed by Arnd Bergmann
Browse files

ARM: dts: artpec: add pcie support 



Add PCIe support to the ARTPEC-6 SoC. This uses the existing
pcie-artpec6 driver.
So, all that is needed is device tree entries in the DTS.

Signed-off-by: default avatarNiklas Cassel <niklas.cassel@axis.com>
Signed-off-by: default avatarJesper Nilsson <jespern@axis.com>
parent 7677796f

arch/arm/boot/dts/artpec6-devboard.dts

+4 −0
Original line number Diff line number Diff line
@@ -46,6 +46,10 @@ 
	status = "okay";

};



&pcie {

	status = "okay";

};



&ethernet {

	status = "okay";

arch/arm/boot/dts/artpec6.dtsi

+28 −1
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ 
		};

	};



	syscon {

	syscon: syscon@f8000000 {

		compatible = "axis,artpec6-syscon", "syscon";

		reg = <0xf8000000 0x48>;

	};
@@ -154,6 +154,33 @@ 
		interrupt-parent = <&intc>;

	};



	pcie: pcie@f8050000 {

		compatible = "axis,artpec6-pcie", "snps,dw-pcie";

		reg = <0xf8050000 0x2000

		       0xf8040000 0x1000

		       0xc0000000 0x2000>;

		reg-names = "dbi", "phy", "config";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

			  /* downstream I/O */

		ranges = <0x81000000 0 0 0xc0002000 0 0x00010000

			  /* non-prefetchable memory */

			  0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;

		num-lanes = <2>;

		bus-range = <0x00 0xff>;

		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "msi";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0x7>;

		interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;

		axis,syscon-pcie = <&syscon>;

		status = "disabled";

	};



	amba@0 {

		compatible = "simple-bus";

		#address-cells = <0x1>;