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Commit be7bc6b9 authored by Maxime Ripard's avatar Maxime Ripard
Browse files

ARM: sunxi: Add the missing clocks to the pinctrl nodes 



The pin controllers also use the two oscillators for debouncing. Add them
to the DTs.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Acked-by: default avatarChen-Yu Tsai <wens@csie.org>
parent 82f2e188

arch/arm/boot/dts/sun4i-a10.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -967,7 +967,8 @@ 
			compatible = "allwinner,sun4i-a10-pinctrl";

			reg = <0x01c20800 0x400>;

			interrupts = <28>;

			clocks = <&apb0_gates 5>;

			clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;

			clock-names = "apb", "hosc", "losc";

			gpio-controller;

			interrupt-controller;

			#interrupt-cells = <3>;

arch/arm/boot/dts/sun5i.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -547,7 +547,8 @@ 
		pio: pinctrl@01c20800 {

			reg = <0x01c20800 0x400>;

			interrupts = <28>;

			clocks = <&apb0_gates 5>;

			clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;

			clock-names = "apb", "hosc", "losc";

			gpio-controller;

			interrupt-controller;

			#interrupt-cells = <3>;

arch/arm/boot/dts/sun6i-a31.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -471,7 +471,8 @@ 
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_APB1_PIO>;

			clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;

			clock-names = "apb", "hosc", "losc";

			gpio-controller;

			interrupt-controller;

			#interrupt-cells = <3>;
@@ -1064,7 +1065,8 @@ 
			reg = <0x01f02c00 0x400>;

			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&apb0_gates 0>;

			clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;

			clock-names = "apb", "hosc", "losc";

			resets = <&apb0_rst 0>;

			gpio-controller;

			interrupt-controller;

arch/arm/boot/dts/sun7i-a20.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -1085,7 +1085,8 @@ 
			compatible = "allwinner,sun7i-a20-pinctrl";

			reg = <0x01c20800 0x400>;

			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&apb0_gates 5>;

			clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;

			clock-names = "apb", "hosc", "losc";

			gpio-controller;

			interrupt-controller;

			#interrupt-cells = <3>;

arch/arm/boot/dts/sun8i-a23-a33.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -266,7 +266,8 @@ 
			/* compatible gets set in SoC specific dtsi file */

			reg = <0x01c20800 0x400>;

			/* interrupts get set in SoC specific dtsi file */

			clocks = <&ccu CLK_BUS_PIO>;

			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;

			clock-names = "apb", "hosc", "losc";

			gpio-controller;

			interrupt-controller;

			#interrupt-cells = <3>;
@@ -575,7 +576,8 @@ 
			compatible = "allwinner,sun8i-a23-r-pinctrl";

			reg = <0x01f02c00 0x400>;

			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&apb0_gates 0>;

			clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;

			clock-names = "apb", "hosc", "losc";

			resets = <&apb0_rst 0>;

			gpio-controller;

			interrupt-controller;