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Commit bdfc1fe8 authored by Sandeep Singh's avatar Sandeep Singh
Browse files

ARM: dts: msm: Add icnss node on atoll 



Add icnss node for atoll, add entry for membase,
CE interrupt vectors.

Change-Id: I5328989f43284353fe418092e570665d417e5d00
Signed-off-by: default avatarSandeep Singh <sandsing@codeaurora.org>
parent 88322861

arch/arm64/boot/dts/qcom/atoll.dtsi

+21 −0
Original line number Diff line number Diff line
@@ -2218,6 +2218,27 @@ 
		#thermal-sensor-cells = <1>;

	};



	icnss: qcom,icnss@18800000 {

		status = "disabled";

		compatible = "qcom,icnss";

		reg = <0x18800000 0x800000>;

		reg-names = "membase";

		interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,

			     <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,

			     <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,

			     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,

			     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,

			     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,

			     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,

			     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,

			     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,

			     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,

			     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */ >,

			     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */ >;

		qcom,smmu-s1-bypass;

		qcom,wlan-msa-fixed-region = <&wlan_fw_mem>;

	};



	qcom,venus@aae0000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0xaae0000 0x4000>;