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Commit bd5c9991 authored by Tony Truong's avatar Tony Truong
Browse files

ARM: dts: msm: add devicetree node for PCIe MSI controller for sm8150 



Add initial devicetree node for PCIe MSI controller which
manages PCIe device INT-X, MSI, and MSI-X on sm8150. Also,
remove dated MSIs from PCIe bus controller node.

Change-Id: I28de4ffeefa24e21853b6cf5de85bd6a85ed7274
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent d35a025d

arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi

+90 −100
Original line number Diff line number Diff line
@@ -35,9 +35,9 @@ 
		ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,

			<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;

		interrupt-parent = <&pcie0>;

		interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

				20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

				36 37>;

		interrupts = <0 1 2 3 4 5>;

		interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",

				"int_global_int";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0xffffffff>;

		interrupt-map = <0 0 0 0 &intc 0 141 0
@@ -45,50 +45,7 @@ 
				0 0 0 2 &intc 0 150 0

				0 0 0 3 &intc 0 151 0

				0 0 0 4 &intc 0 152 0

				0 0 0 5 &intc 0 140 0

				0 0 0 6 &intc 0 768 0

				0 0 0 7 &intc 0 769 0

				0 0 0 8 &intc 0 770 0

				0 0 0 9 &intc 0 771 0

				0 0 0 10 &intc 0 772 0

				0 0 0 11 &intc 0 773 0

				0 0 0 12 &intc 0 774 0

				0 0 0 13 &intc 0 775 0

				0 0 0 14 &intc 0 776 0

				0 0 0 15 &intc 0 777 0

				0 0 0 16 &intc 0 778 0

				0 0 0 17 &intc 0 779 0

				0 0 0 18 &intc 0 780 0

				0 0 0 19 &intc 0 781 0

				0 0 0 20 &intc 0 782 0

				0 0 0 21 &intc 0 783 0

				0 0 0 22 &intc 0 784 0

				0 0 0 23 &intc 0 785 0

				0 0 0 24 &intc 0 786 0

				0 0 0 25 &intc 0 787 0

				0 0 0 26 &intc 0 788 0

				0 0 0 27 &intc 0 789 0

				0 0 0 28 &intc 0 790 0

				0 0 0 29 &intc 0 791 0

				0 0 0 30 &intc 0 792 0

				0 0 0 31 &intc 0 793 0

				0 0 0 32 &intc 0 794 0

				0 0 0 33 &intc 0 795 0

				0 0 0 34 &intc 0 796 0

				0 0 0 35 &intc 0 797 0

				0 0 0 36 &intc 0 798 0

				0 0 0 37 &intc 0 799 0>;



		interrupt-names = "int_msi", "int_a", "int_b", "int_c",

				"int_d", "int_global_int",

				"msi_0", "msi_1", "msi_2", "msi_3",

				"msi_4", "msi_5", "msi_6", "msi_7",

				"msi_8", "msi_9", "msi_10", "msi_11",

				"msi_12", "msi_13", "msi_14", "msi_15",

				"msi_16", "msi_17", "msi_18", "msi_19",

				"msi_20", "msi_21", "msi_22", "msi_23",

				"msi_24", "msi_25", "msi_26", "msi_27",

				"msi_28", "msi_29", "msi_30", "msi_31";

				0 0 0 5 &intc 0 140 0>;



		qcom,phy-sequence = <0x0840 0x03 0x0

				0x0094 0x08 0x0
@@ -208,6 +165,8 @@ 
		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX

						RPMH_REGULATOR_LEVEL_NOM 0>;



		msi-parent = <&pcie0_msi>;



		qcom,no-l0s-supported;



		qcom,ep-latency = <10>;
@@ -221,9 +180,6 @@ 


		linux,pci-domain = <0>;



		qcom,msi-gicm-addr = <0x17a00040>;

		qcom,msi-gicm-base = <0x320>;



		qcom,pcie-phy-ver = <0x40>;

		qcom,use-19p2mhz-aux-clk;
@@ -286,6 +242,45 @@ 
		};

	};



	pcie0_msi: qcom,pcie0_msi@17a00040 {

		compatible = "qcom,pci-msi";

		msi-controller;

		reg = <0x17a00040 0x0>;

		interrupt-parent = <&pdc>;

		interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;

	};



	pcie1: qcom,pcie@1c08000 {

		compatible = "qcom,pci-msm";

		cell-index = <1>;
@@ -307,9 +302,9 @@ 
		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,

			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;

		interrupt-parent = <&pcie1>;

		interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

				20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

				36 37>;

		interrupts = <0 1 2 3 4 5>;

		interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",

				"int_global_int";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0xffffffff>;

		interrupt-map = <0 0 0 0 &intc 0 307 0
@@ -317,50 +312,7 @@ 
				0 0 0 2 &intc 0 435 0

				0 0 0 3 &intc 0 438 0

				0 0 0 4 &intc 0 439 0

				0 0 0 5 &intc 0 306 0

				0 0 0 6 &intc 0 800 0

				0 0 0 7 &intc 0 801 0

				0 0 0 8 &intc 0 802 0

				0 0 0 9 &intc 0 803 0

				0 0 0 10 &intc 0 804 0

				0 0 0 11 &intc 0 805 0

				0 0 0 12 &intc 0 806 0

				0 0 0 13 &intc 0 807 0

				0 0 0 14 &intc 0 808 0

				0 0 0 15 &intc 0 809 0

				0 0 0 16 &intc 0 810 0

				0 0 0 17 &intc 0 811 0

				0 0 0 18 &intc 0 812 0

				0 0 0 19 &intc 0 813 0

				0 0 0 20 &intc 0 814 0

				0 0 0 21 &intc 0 815 0

				0 0 0 22 &intc 0 816 0

				0 0 0 23 &intc 0 817 0

				0 0 0 24 &intc 0 818 0

				0 0 0 25 &intc 0 819 0

				0 0 0 26 &intc 0 820 0

				0 0 0 27 &intc 0 821 0

				0 0 0 28 &intc 0 822 0

				0 0 0 29 &intc 0 823 0

				0 0 0 30 &intc 0 824 0

				0 0 0 31 &intc 0 825 0

				0 0 0 32 &intc 0 826 0

				0 0 0 33 &intc 0 827 0

				0 0 0 34 &intc 0 828 0

				0 0 0 35 &intc 0 829 0

				0 0 0 36 &intc 0 830 0

				0 0 0 37 &intc 0 831 0>;



		interrupt-names = "int_msi", "int_a", "int_b", "int_c",

				"int_d", "int_global_int",

				"msi_0", "msi_1", "msi_2", "msi_3",

				"msi_4", "msi_5", "msi_6", "msi_7",

				"msi_8", "msi_9", "msi_10", "msi_11",

				"msi_12", "msi_13", "msi_14", "msi_15",

				"msi_16", "msi_17", "msi_18", "msi_19",

				"msi_20", "msi_21", "msi_22", "msi_23",

				"msi_24", "msi_25", "msi_26", "msi_27",

				"msi_28", "msi_29", "msi_30", "msi_31";

				0 0 0 5 &intc 0 306 0>;



		qcom,phy-sequence = <0x0a40 0x03 0x0

				0x0010 0x00 0x0
@@ -530,6 +482,8 @@ 
		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX

						RPMH_REGULATOR_LEVEL_NOM 0>;



		msi-parent = <&pcie1_msi>;



		qcom,no-l0s-supported;



		qcom,ep-latency = <10>;
@@ -543,9 +497,6 @@ 


		linux,pci-domain = <1>;



		qcom,msi-gicm-addr = <0x17a00040>;

		qcom,msi-gicm-base = <0x340>;



		qcom,pcie-phy-ver = <0x40>;

		qcom,use-19p2mhz-aux-clk;
@@ -607,4 +558,43 @@ 
			reg = <0 0 0 0 0>;

		};

	};



	pcie1_msi: qcom,pcie1_msi@17a00040 {

		compatible = "qcom,pci-msi";

		msi-controller;

		reg = <0x17a00040 0x0>;

		interrupt-parent = <&pdc>;

		interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 801 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 802 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 803 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 804 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 805 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 806 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 807 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 808 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 809 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 810 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 811 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 812 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 813 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 814 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 815 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 816 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 817 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 818 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 819 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 820 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 821 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 822 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 823 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 824 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 825 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 826 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 827 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 828 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 829 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 830 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 831 IRQ_TYPE_EDGE_RISING>;

	};

};

drivers/pci/host/pci-msm.c

+6 −0
Original line number Diff line number Diff line
@@ -4437,6 +4437,12 @@ int msm_pcie_enumerate(u32 rc_idx) 
				goto out;

			}



			if (IS_ENABLED(CONFIG_PCI_MSM_MSI)) {

				ret = msm_msi_init(&dev->pdev->dev);

				if (ret)

					return ret;

			}



			list_splice_init(&res, &bridge->windows);

			bridge->dev.parent = &dev->pdev->dev;

			bridge->sysdata = dev;