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Commit bd5bb6c4 authored by Kai Liu's avatar Kai Liu
Browse files

ARM: dts: msm: Update MSI interrupts for sa8195p 



Update MSI interrupts for sa8195p such that base
interrupt is 32 bit aligned.

Change-Id: I3dc56bb74887f63400f2e54b20188366bf7e3a30
Signed-off-by: default avatarKai Liu <kaliu@codeaurora.org>
parent b99e6929

arch/arm64/boot/dts/qcom/sa8195p-pcie.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -248,7 +248,11 @@ 
		msi-controller;

		reg = <0x17a00040 0x0>;

		interrupt-parent = <&pdc>;

		interrupts = <GIC_SPI 868 IRQ_TYPE_EDGE_RISING>,

		interrupts = <GIC_SPI 864 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 865 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 866 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 867 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 868 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 869 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 870 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 871 IRQ_TYPE_EDGE_RISING>,
@@ -275,11 +279,7 @@ 
			<GIC_SPI 892 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 893 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 894 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 895 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 896 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 897 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 898 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 899 IRQ_TYPE_EDGE_RISING>;

			<GIC_SPI 895 IRQ_TYPE_EDGE_RISING>;

	};



	pcie1: qcom,pcie@1c08000 {