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Commit bd31b859 authored by Thomas Gleixner's avatar Thomas Gleixner Committed by Ingo Molnar
Browse files

locking, ARM: Annotate low level hw locks as raw 



Annotate the low level hardware locks which must not be preempted.

In mainline this change documents the low level nature of
the lock - otherwise there's no functional difference. Lockdep
and Sparse checking will work as usual.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent a1741e7f

arch/arm/common/gic.c

+13 −13
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ 
#include <asm/mach/irq.h>

#include <asm/hardware/gic.h>



static DEFINE_SPINLOCK(irq_controller_lock);

static DEFINE_RAW_SPINLOCK(irq_controller_lock);



/* Address of GIC 0 CPU interface */

void __iomem *gic_cpu_base_addr __read_mostly;
@@ -82,30 +82,30 @@ static void gic_mask_irq(struct irq_data *d) 
{

	u32 mask = 1 << (d->irq % 32);



	spin_lock(&irq_controller_lock);

	raw_spin_lock(&irq_controller_lock);

	writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);

	if (gic_arch_extn.irq_mask)

		gic_arch_extn.irq_mask(d);

	spin_unlock(&irq_controller_lock);

	raw_spin_unlock(&irq_controller_lock);

}



static void gic_unmask_irq(struct irq_data *d)

{

	u32 mask = 1 << (d->irq % 32);



	spin_lock(&irq_controller_lock);

	raw_spin_lock(&irq_controller_lock);

	if (gic_arch_extn.irq_unmask)

		gic_arch_extn.irq_unmask(d);

	writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);

	spin_unlock(&irq_controller_lock);

	raw_spin_unlock(&irq_controller_lock);

}



static void gic_eoi_irq(struct irq_data *d)

{

	if (gic_arch_extn.irq_eoi) {

		spin_lock(&irq_controller_lock);

		raw_spin_lock(&irq_controller_lock);

		gic_arch_extn.irq_eoi(d);

		spin_unlock(&irq_controller_lock);

		raw_spin_unlock(&irq_controller_lock);

	}



	writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
@@ -129,7 +129,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) 
	if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)

		return -EINVAL;



	spin_lock(&irq_controller_lock);

	raw_spin_lock(&irq_controller_lock);



	if (gic_arch_extn.irq_set_type)

		gic_arch_extn.irq_set_type(d, type);
@@ -154,7 +154,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) 
	if (enabled)

		writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);



	spin_unlock(&irq_controller_lock);

	raw_spin_unlock(&irq_controller_lock);



	return 0;

}
@@ -182,10 +182,10 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 
	mask = 0xff << shift;

	bit = 1 << (cpu + shift);



	spin_lock(&irq_controller_lock);

	raw_spin_lock(&irq_controller_lock);

	val = readl_relaxed(reg) & ~mask;

	writel_relaxed(val | bit, reg);

	spin_unlock(&irq_controller_lock);

	raw_spin_unlock(&irq_controller_lock);



	return IRQ_SET_MASK_OK;

}
@@ -215,9 +215,9 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) 


	chained_irq_enter(chip, desc);



	spin_lock(&irq_controller_lock);

	raw_spin_lock(&irq_controller_lock);

	status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);

	spin_unlock(&irq_controller_lock);

	raw_spin_unlock(&irq_controller_lock);



	gic_irq = (status & 0x3ff);

	if (gic_irq == 1023)

arch/arm/include/asm/dma.h

+3 −3
Original line number Diff line number Diff line
@@ -34,18 +34,18 @@ 
#define DMA_MODE_CASCADE 0xc0

#define DMA_AUTOINIT	 0x10



extern spinlock_t  dma_spin_lock;

extern raw_spinlock_t  dma_spin_lock;



static inline unsigned long claim_dma_lock(void)

{

	unsigned long flags;

	spin_lock_irqsave(&dma_spin_lock, flags);

	raw_spin_lock_irqsave(&dma_spin_lock, flags);

	return flags;

}



static inline void release_dma_lock(unsigned long flags)

{

	spin_unlock_irqrestore(&dma_spin_lock, flags);

	raw_spin_unlock_irqrestore(&dma_spin_lock, flags);

}



/* Clear the 'DMA Pointer Flip Flop'.

arch/arm/include/asm/mmu.h

+2 −2
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 
typedef struct {

#ifdef CONFIG_CPU_HAS_ASID

	unsigned int id;

	spinlock_t id_lock;

	raw_spinlock_t id_lock;

#endif

	unsigned int kvm_seq;

} mm_context_t;
@@ -16,7 +16,7 @@ typedef struct { 


/* init_mm.context.id_lock should be initialized. */

#define INIT_MM_CONTEXT(name)                                                 \

	.context.id_lock    = __SPIN_LOCK_UNLOCKED(name.context.id_lock),

	.context.id_lock    = __RAW_SPIN_LOCK_UNLOCKED(name.context.id_lock),

#else

#define ASID(mm)	(0)

#endif

arch/arm/kernel/dma.c

+1 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 


#include <asm/mach/dma.h>



DEFINE_SPINLOCK(dma_spin_lock);

DEFINE_RAW_SPINLOCK(dma_spin_lock);

EXPORT_SYMBOL(dma_spin_lock);



static dma_t *dma_chan[MAX_DMA_CHANNELS];

arch/arm/kernel/smp.c

+3 −3
Original line number Diff line number Diff line
@@ -538,7 +538,7 @@ static void percpu_timer_stop(void) 
}

#endif



static DEFINE_SPINLOCK(stop_lock);

static DEFINE_RAW_SPINLOCK(stop_lock);



/*

 * ipi_cpu_stop - handle IPI from smp_send_stop()
@@ -547,10 +547,10 @@ static void ipi_cpu_stop(unsigned int cpu) 
{

	if (system_state == SYSTEM_BOOTING ||

	    system_state == SYSTEM_RUNNING) {

		spin_lock(&stop_lock);

		raw_spin_lock(&stop_lock);

		printk(KERN_CRIT "CPU%u: stopping\n", cpu);

		dump_stack();

		spin_unlock(&stop_lock);

		raw_spin_unlock(&stop_lock);

	}



	set_cpu_online(cpu, false);