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Commit bcb88aca authored by Shefali Jain's avatar Shefali Jain
Browse files

clk: qcom: clk-pll: Support list_registers callback for HF PLL 



For hf pll, register content is required to be display
for debug purpose. Add support for the same by adding
list_register clock ops to clk_pll_hf_ops.

Change-Id: I3e392668542e99e09f420f8c9a6ce4b9172e2eb8
Signed-off-by: default avatarShefali Jain <shefjain@codeaurora.org>
parent 848831da

drivers/clk/qcom/clk-pll.c

+25 −0
Original line number Diff line number Diff line
@@ -372,11 +372,36 @@ clk_pll_hf_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 
	return 0;

}



static void clk_pll_hf_list_registers(struct seq_file *f, struct clk_hw *hw)

{

	struct clk_pll *pll = to_clk_pll(hw);

	int size, i, val;



	static struct clk_register_data data[] = {

		{"PLL_MODE", 0x0},

		{"PLL_L_VAL", 0x4},

		{"PLL_M_VAL", 0x8},

		{"PLL_N_VAL", 0xC},

		{"PLL_USER_CTL", 0x10},

		{"PLL_CONFIG_CTL", 0x14},

		{"PLL_STATUS_CTL", 0x1C},

	};



	size = ARRAY_SIZE(data);



	for (i = 0; i < size; i++) {

		regmap_read(pll->clkr.regmap, pll->mode_reg + data[i].offset,

									&val);

		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);

	}

}



const struct clk_ops clk_pll_hf_ops = {

	.enable = clk_pll_sr2_enable,

	.disable = clk_pll_disable,

	.set_rate = clk_pll_hf_set_rate,

	.recalc_rate = clk_pll_recalc_rate,

	.determine_rate = clk_pll_determine_rate,

	.list_registers = clk_pll_hf_list_registers,

};

EXPORT_SYMBOL(clk_pll_hf_ops);