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Commit bc5378fc authored by Max Filippov's avatar Max Filippov Committed by Chris Zankel
Browse files

xtensa: reorganize SR referencing 



- reference SRs by names where possible, not by numbers;
- get rid of __stringify around SR names where possible;
- remove unneeded SR names from asm/regs.h;
- add SREG_ prefix to remaining SR names;

Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
Signed-off-by: default avatarChris Zankel <chris@zankel.net>
parent f4349b6e

arch/xtensa/boot/boot-redboot/bootstrap.S

+4 −4
Original line number Diff line number Diff line
@@ -51,17 +51,17 @@ _start: 
	/* 'reset' window registers */



	movi	a4, 1

	wsr	a4, PS

	wsr	a4, ps

	rsync



	rsr	a5, WINDOWBASE

	rsr	a5, windowbase

	ssl	a5

	sll	a4, a4

	wsr	a4, WINDOWSTART

	wsr	a4, windowstart

	rsync



	movi	a4, 0x00040000

	wsr	a4, PS

	wsr	a4, ps

	rsync



	/* copy the loader to its address

arch/xtensa/include/asm/atomic.h

+6 −6
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ static inline void atomic_add(int i, atomic_t * v) 
	"l32i    %0, %2, 0              \n\t"

	"add     %0, %0, %1             \n\t"

	"s32i    %0, %2, 0              \n\t"

	"wsr     a15, "__stringify(PS)"       \n\t"

	"wsr     a15, ps                \n\t"

	"rsync                          \n"

	: "=&a" (vval)

	: "a" (i), "a" (v)
@@ -97,7 +97,7 @@ static inline void atomic_sub(int i, atomic_t *v) 
	"l32i    %0, %2, 0              \n\t"

	"sub     %0, %0, %1             \n\t"

	"s32i    %0, %2, 0              \n\t"

	"wsr     a15, "__stringify(PS)"       \n\t"

	"wsr     a15, ps                \n\t"

	"rsync                          \n"

	: "=&a" (vval)

	: "a" (i), "a" (v)
@@ -118,7 +118,7 @@ static inline int atomic_add_return(int i, atomic_t * v) 
	"l32i    %0, %2, 0             \n\t"

	"add     %0, %0, %1            \n\t"

	"s32i    %0, %2, 0             \n\t"

	"wsr     a15, "__stringify(PS)"      \n\t"

	"wsr     a15, ps               \n\t"

	"rsync                         \n"

	: "=&a" (vval)

	: "a" (i), "a" (v)
@@ -137,7 +137,7 @@ static inline int atomic_sub_return(int i, atomic_t * v) 
	"l32i    %0, %2, 0             \n\t"

	"sub     %0, %0, %1            \n\t"

	"s32i    %0, %2, 0             \n\t"

	"wsr     a15, "__stringify(PS)"       \n\t"

	"wsr     a15, ps               \n\t"

	"rsync                         \n"

	: "=&a" (vval)

	: "a" (i), "a" (v)
@@ -260,7 +260,7 @@ static inline void atomic_clear_mask(unsigned int mask, atomic_t *v) 
	"xor     %1, %4, %3            \n\t"

	"and     %0, %0, %4            \n\t"

	"s32i    %0, %2, 0             \n\t"

	"wsr     a15, "__stringify(PS)"      \n\t"

	"wsr     a15, ps               \n\t"

	"rsync                         \n"

	: "=&a" (vval), "=a" (mask)

	: "a" (v), "a" (all_f), "1" (mask)
@@ -277,7 +277,7 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v) 
	"l32i    %0, %2, 0             \n\t"

	"or      %0, %0, %1            \n\t"

	"s32i    %0, %2, 0             \n\t"

	"wsr     a15, "__stringify(PS)"       \n\t"

	"wsr     a15, ps               \n\t"

	"rsync                         \n"

	: "=&a" (vval)

	: "a" (mask), "a" (v)

arch/xtensa/include/asm/cacheflush.h

+1 −1
Original line number Diff line number Diff line
@@ -165,7 +165,7 @@ extern void copy_from_user_page(struct vm_area_struct*, struct page*, 
static inline u32 xtensa_get_cacheattr(void)

{

	u32 r;

	asm volatile("	rsr %0, CACHEATTR" : "=a"(r));

	asm volatile("	rsr %0, cacheattr" : "=a"(r));

	return r;

}

arch/xtensa/include/asm/cmpxchg.h

+2 −2
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ __cmpxchg_u32(volatile int *p, int old, int new) 
		       "bne	%0, %2, 1f             \n\t"

		       "s32i    %3, %1, 0              \n\t"

		       "1:                             \n\t"

		       "wsr     a15, "__stringify(PS)" \n\t"

		       "wsr     a15, ps                \n\t"

		       "rsync                          \n\t"

		       : "=&a" (old)

		       : "a" (p), "a" (old), "r" (new)
@@ -97,7 +97,7 @@ static inline unsigned long xchg_u32(volatile int * m, unsigned long val) 
  __asm__ __volatile__("rsil    a15, "__stringify(LOCKLEVEL)"\n\t"

		       "l32i    %0, %1, 0              \n\t"

		       "s32i    %2, %1, 0              \n\t"

		       "wsr     a15, "__stringify(PS)" \n\t"

		       "wsr     a15, ps                \n\t"

		       "rsync                          \n\t"

		       : "=&a" (tmp)

		       : "a" (m), "a" (val)

arch/xtensa/include/asm/coprocessor.h

+2 −3
Original line number Diff line number Diff line
@@ -94,11 +94,10 @@ 
#if XCHAL_HAVE_CP



#define RSR_CPENABLE(x)	do {						  \

	__asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \

	__asm__ __volatile__("rsr %0, cpenable" : "=a" (x));		  \

	} while(0);

#define WSR_CPENABLE(x)	do {						  \

  	__asm__ __volatile__("wsr %0," __stringify(CPENABLE) "; rsync" 	  \

	    		     :: "a" (x));				  \

	__asm__ __volatile__("wsr %0, cpenable; rsync" :: "a" (x));	  \

	} while(0);



#endif /* XCHAL_HAVE_CP */