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Commit bbf59266 authored by Hareesh Gundu's avatar Hareesh Gundu Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Add LLC support for A608 GPU 



For A608 GPU, SCID configuration registers have moved from CX_MISC
to GBIF register space. And the GPU HTW SCID is configured via
NoC override in XBL image.

And, LLC page attributes override through GBIF is not supported
with MMU-500. Skip this override setting for A608 which
has the GBIF and MMU-500.

Also, use DOMAIN_ATTR_USE_LLC_NWA attribute for GPU traffic and
page table walk to be read-allocate, write-no-allocate.

Change-Id: I4d01d7929912c43cdf928b71eb3a5a988a54922a
Signed-off-by: default avatarHareesh Gundu <hareeshg@codeaurora.org>
Signed-off-by: default avatarAkhil P Oommen <akhilpo@codeaurora.org>
parent d96627d1

drivers/gpu/msm/adreno_a6xx.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -1627,7 +1627,7 @@ static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev) 
		gpu_cntl1_val = (gpu_cntl1_val << A6XX_GPU_LLC_SCID_NUM_BITS)

		gpu_cntl1_val = (gpu_cntl1_val << A6XX_GPU_LLC_SCID_NUM_BITS)

			| gpu_scid;

			| gpu_scid;





	if (adreno_is_a640(adreno_dev)) {

	if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev)) {

		kgsl_regrmw(KGSL_DEVICE(adreno_dev), A6XX_GBIF_SCACHE_CNTL1,

		kgsl_regrmw(KGSL_DEVICE(adreno_dev), A6XX_GBIF_SCACHE_CNTL1,

			A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val);

			A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val);

	} else {

	} else {
@@ -1654,7 +1654,7 @@ static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev) 
	 * On A640, the GPUHTW SCID is configured via a NoC override in the

	 * On A640, the GPUHTW SCID is configured via a NoC override in the

	 * XBL image.

	 * XBL image.

	 */

	 */

	if (adreno_is_a640(adreno_dev))

	if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev))

		return;

		return;





	gpuhtw_scid = adreno_llc_get_scid(adreno_dev->gpuhtw_llc_slice);

	gpuhtw_scid = adreno_llc_get_scid(adreno_dev->gpuhtw_llc_slice);
@@ -1678,7 +1678,7 @@ static void a6xx_llc_enable_overrides(struct adreno_device *adreno_dev) 
	 * Attributes override through GBIF is not supported with MMU-500.

	 * Attributes override through GBIF is not supported with MMU-500.

	 * Attributes are used as configured through SMMU pagetable entries.

	 * Attributes are used as configured through SMMU pagetable entries.

	 */

	 */

	if (adreno_is_a640(adreno_dev))

	if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev))

		return;

		return;





	/*

	/*

drivers/gpu/msm/kgsl_iommu.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -1182,7 +1182,7 @@ void _enable_gpuhtw_llc(struct kgsl_mmu *mmu, struct kgsl_iommu_pt *iommu_pt) 
		return;

		return;





	/* Domain attribute to enable system cache for GPU pagetable walks */

	/* Domain attribute to enable system cache for GPU pagetable walks */

	if (adreno_is_a640(adreno_dev))

	if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev))

		ret = iommu_domain_set_attr(iommu_pt->domain,

		ret = iommu_domain_set_attr(iommu_pt->domain,

			DOMAIN_ATTR_USE_LLC_NWA, &gpuhtw_llc_enable);

			DOMAIN_ATTR_USE_LLC_NWA, &gpuhtw_llc_enable);

	else

	else