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Commit bbb63668 authored by Jeevan Shriram's avatar Jeevan Shriram
Browse files

ARM: dts: msm: Enable PSCI enable method for SDMSHRIKE 



Enable PSCI enable method for the CPUs for supporting
SMP mode on SDMSHRIKE target.

Change-Id: Idf10fc8c16d3ecf58f0401820bc6ef1fa8ecade0
Signed-off-by: default avatarJeevan Shriram <jshriram@codeaurora.org>
parent f0a4ec7d

arch/arm64/boot/dts/qcom/sdmshrike.dtsi

+13 −16
Original line number Diff line number Diff line
@@ -44,8 +44,7 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			enable-method = "psci";

			cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {
@@ -66,8 +65,7 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			enable-method = "psci";

			cache-size = <0x8000>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {
@@ -82,8 +80,7 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x200>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			enable-method = "psci";

			cache-size = <0x8000>;

			next-level-cache = <&L2_2>;

			L2_2: l2-cache {
@@ -98,8 +95,7 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x300>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			enable-method = "psci";

			cache-size = <0x8000>;

			next-level-cache = <&L2_3>;

			L2_3: l2-cache {
@@ -114,8 +110,7 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x400>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			enable-method = "psci";

			cache-size = <0x20000>;

			next-level-cache = <&L2_4>;

			L2_4: l2-cache {
@@ -130,8 +125,7 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x500>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			enable-method = "psci";

			cache-size = <0x20000>;

			next-level-cache = <&L2_5>;

			L2_5: l2-cache {
@@ -146,8 +140,7 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x600>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			enable-method = "psci";

			cache-size = <0x20000>;

			next-level-cache = <&L2_6>;

			L2_6: l2-cache {
@@ -162,8 +155,7 @@ 
			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x700>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x90000000>;

			enable-method = "psci";

			cache-size = <0x20000>;

			next-level-cache = <&L2_7>;

			L2_7: l2-cache {
@@ -211,6 +203,11 @@ 
				};

			};

		};



		psci {

			compatible = "arm,psci-1.0";

			method = "smc";

		};

	};



	reserved-memory {