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Commit baaa7237 authored by Mark Rutland's avatar Mark Rutland Committed by Will Deacon
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arm64: zero GPRs upon entry from EL0 



We can zero GPRs x0 - x29 upon entry from EL0 to make it harder for
userspace to control values consumed by speculative gadgets.

We don't blat x30, since this is stashed much later, and we'll blat it
before invoking C code.

Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 99ed3ed0

arch/arm64/kernel/entry.S

+7 −1
Original line number Diff line number Diff line
@@ -53,6 +53,12 @@ 
#endif

	.endm



	.macro	clear_gp_regs

	.irp	n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29

	mov	x\n, xzr

	.endr

	.endm



/*

 * Bad Abort numbers

 *-----------------
@@ -169,6 +175,7 @@ alternative_cb_end 
	stp	x28, x29, [sp, #16 * 14]



	.if	\el == 0

	clear_gp_regs

	mrs	x21, sp_el0

	ldr_this_cpu	tsk, __entry_task, x20	// Ensure MDSCR_EL1.SS is clear,

	ldr	x19, [tsk, #TSK_TI_FLAGS]	// since we can unmask debug
@@ -176,7 +183,6 @@ alternative_cb_end 


	apply_ssbd 1, x22, x23



	mov	x29, xzr			// fp pointed to user-space

	.else

	add	x21, sp, #S_FRAME_SIZE

	get_thread_info tsk