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Commit b94ee062 authored by Olof Johansson's avatar Olof Johansson
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Merge branch 'depends/rmk/devel-stable' into next/boards

parents dc47ce90 3bdc3484
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+5 −6
Original line number Original line Diff line number Diff line
@@ -51,15 +51,14 @@ ffc00000 ffefffff DMA memory mapping region. Memory returned
ff000000	ffbfffff	Reserved for future expansion of DMA
ff000000	ffbfffff	Reserved for future expansion of DMA
				mapping region.
				mapping region.


VMALLOC_END	feffffff	Free for platform use, recommended.
				VMALLOC_END must be aligned to a 2MB
				boundary.

VMALLOC_START	VMALLOC_END-1	vmalloc() / ioremap() space.
VMALLOC_START	VMALLOC_END-1	vmalloc() / ioremap() space.
				Memory returned by vmalloc/ioremap will
				Memory returned by vmalloc/ioremap will
				be dynamically placed in this region.
				be dynamically placed in this region.
				VMALLOC_START may be based upon the value
				Machine specific static mappings are also
				of the high_memory variable.
				located here through iotable_init().
				VMALLOC_START is based upon the value
				of the high_memory variable, and VMALLOC_END
				is equal to 0xff000000.


PAGE_OFFSET	high_memory-1	Kernel direct-mapped RAM region.
PAGE_OFFSET	high_memory-1	Kernel direct-mapped RAM region.
				This maps the platforms RAM, and typically
				This maps the platforms RAM, and typically
+4 −0
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@@ -42,6 +42,10 @@ Optional
- interrupts	: Interrupt source of the parent interrupt controller. Only
- interrupts	: Interrupt source of the parent interrupt controller. Only
  present on secondary GICs.
  present on secondary GICs.


- cpu-offset	: per-cpu offset within the distributor and cpu interface
  regions, used when the GIC doesn't have banked registers. The offset is
  cpu-offset * cpu-nr.

Example:
Example:


	intc: interrupt-controller@fff11000 {
	intc: interrupt-controller@fff11000 {
+29 −0
Original line number Original line Diff line number Diff line
* ARM Vectored Interrupt Controller

One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM
system for interrupt routing.  For multiple controllers they can either be
nested or have the outputs wire-OR'd together.

Required properties:

- compatible : should be one of
	"arm,pl190-vic"
	"arm,pl192-vic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : The number of cells to define the interrupts.  Must be 1 as
  the VIC has no configuration options for interrupt sources.  The cell is a u32
  and defines the interrupt number.
- reg : The register bank for the VIC.

Optional properties:

- interrupts : Interrupt source for parent controllers if the VIC is nested.

Example:

	vic0: interrupt-controller@60000 {
		compatible = "arm,pl192-vic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x60000 0x1000>;
	};
+2 −2
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@@ -1971,7 +1971,7 @@ endchoice


config XIP_KERNEL
config XIP_KERNEL
	bool "Kernel Execute-In-Place from ROM"
	bool "Kernel Execute-In-Place from ROM"
	depends on !ZBOOT_ROM
	depends on !ZBOOT_ROM && !ARM_LPAE
	help
	help
	  Execute-In-Place allows the kernel to run from non-volatile storage
	  Execute-In-Place allows the kernel to run from non-volatile storage
	  directly addressable by the CPU, such as NOR flash. This saves RAM
	  directly addressable by the CPU, such as NOR flash. This saves RAM
@@ -2001,7 +2001,7 @@ config XIP_PHYS_ADDR


config KEXEC
config KEXEC
	bool "Kexec system call (EXPERIMENTAL)"
	bool "Kexec system call (EXPERIMENTAL)"
	depends on EXPERIMENTAL
	depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
	help
	help
	  kexec is a system call that implements the ability to shutdown your
	  kexec is a system call that implements the ability to shutdown your
	  current kernel, and to start another kernel.  It is like a reboot
	  current kernel, and to start another kernel.  It is like a reboot
+1 −0
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@@ -659,6 +659,7 @@ __armv7_mmu_cache_on:
		mcrne	p15, 0, r3, c2, c0, 0	@ load page table pointer
		mcrne	p15, 0, r3, c2, c0, 0	@ load page table pointer
		mcrne	p15, 0, r1, c3, c0, 0	@ load domain access control
		mcrne	p15, 0, r1, c3, c0, 0	@ load domain access control
#endif
#endif
		mcr	p15, 0, r0, c7, c5, 4	@ ISB
		mcr	p15, 0, r0, c1, c0, 0	@ load control register
		mcr	p15, 0, r0, c1, c0, 0	@ load control register
		mrc	p15, 0, r0, c1, c0, 0	@ and read it back
		mrc	p15, 0, r0, c1, c0, 0	@ and read it back
		mov	r0, #0
		mov	r0, #0
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