Commit b9001114 authored Nov 19, 2015 by Maarten Lankhorst

drm/i915/skl: Update watermarks before the crtc is disabled.

On skylake some of the registers are only writable when the correct
power wells are enabled. Because of this watermarks have to be updated
before the crtc turns off, or you get unclaimed register read and write
warnings.

This patch needs to be modified slightly to apply to -fixes.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181


Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: stable@vger.kernel.org
Cc: Matt Roper <matthew.d.roper@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447945645-32005-4-git-send-email-maarten.lankhorst@linux.intel.com


Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>

parent 92826fcd

drivers/gpu/drm/i915/intel_display.c

+4 −1

Original line number	Original line	Diff line number	Diff line
	@@ -4804,7 +4804,7 @@ static void intel_post_plane_update(struct intel_crtc *crtc)

	crtc->wm.cxsr_allowed = true;		crtc->wm.cxsr_allowed = true;

	if (pipe_config->wm_changed)		if (pipe_config->wm_changed && pipe_config->base.active)
	intel_update_watermarks(&crtc->base);		intel_update_watermarks(&crtc->base);

	if (atomic->update_fbc)		if (atomic->update_fbc)
	@@ -13421,6 +13421,9 @@ static int intel_atomic_commit(struct drm_device *dev,
	*/		*/
	intel_check_cpu_fifo_underruns(dev_priv);		intel_check_cpu_fifo_underruns(dev_priv);
	intel_check_pch_fifo_underruns(dev_priv);		intel_check_pch_fifo_underruns(dev_priv);

			if (!crtc->state->active)
			intel_update_watermarks(crtc);
	}		}
	}		}