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Commit b8a71080 authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'drm-intel-next-2018-05-14' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



Last drm/i915 changes for v4.18:

- NV12 enabling (Chandra, Maarten)
- ICL workarounds (Oscar)
- ICL basic DPLL enabling (Paulo)
- GVT updates
- DP link config refactoring (Jani)
- Module parameter to override DMC firmware (Jani)
- PSR updates (José, DK, Daniel, Ville)
- ICL DP vswing programming (Manasi)
- ICL DBuf slice updates (Mahesh)
- Selftest fixes and updates (Chris, Matthew, Oscar)
- Execlist fixes and updates (Chris)
- Stolen memory first 4k fix (Hans de Goede)
- wait_for fixes (Mika)
- Tons of GEM improvements (Chris)
- Plenty of other fixes and improvements (Everyone)
- Crappy changelog (Me)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

# gpg: Signature made Mon 14 May 2018 11:04:24 PM AEST
# gpg:                using RSA key D398079D26ABEE6F
# gpg: Good signature from "Jani Nikula <jani.nikula@intel.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 1565 A65B 77B0 632E 1124  E59C D398 079D 26AB EE6F

# Conflicts:
#	drivers/gpu/drm/i915/intel_lrc.c
#	drivers/gpu/drm/i915/intel_sprite.c
Link: https://patchwork.freedesktop.org/patch/msgid/87k1s51bvw.fsf@intel.com
parents 2045b224 01f83786

drivers/gpu/drm/drm_atomic.c

+7 −3
Original line number Diff line number Diff line
@@ -1716,11 +1716,15 @@ int drm_atomic_check_only(struct drm_atomic_state *state) 
		}

	}



	if (config->funcs->atomic_check)

	if (config->funcs->atomic_check) {

		ret = config->funcs->atomic_check(state->dev, state);



	if (ret)

		if (ret) {

			DRM_DEBUG_ATOMIC("atomic driver check for %p failed: %d\n",

					 state, ret);

			return ret;

		}

	}



	if (!state->allow_modeset) {

		for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/i915/Makefile

+7 −2
Original line number Diff line number Diff line
@@ -18,6 +18,10 @@ subdir-ccflags-y += $(call cc-disable-warning, type-limits) 
subdir-ccflags-y += $(call cc-disable-warning, missing-field-initializers)

subdir-ccflags-y += $(call cc-disable-warning, implicit-fallthrough)

subdir-ccflags-y += $(call cc-disable-warning, unused-but-set-variable)

# clang warnings

subdir-ccflags-y += $(call cc-disable-warning, sign-compare)

subdir-ccflags-y += $(call cc-disable-warning, sometimes-uninitialized)

subdir-ccflags-y += $(call cc-disable-warning, initializer-overrides)

subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror



# Fine grained warnings disable
@@ -67,11 +71,11 @@ i915-y += i915_cmd_parser.o \ 
	  i915_gem_shrinker.o \

	  i915_gem_stolen.o \

	  i915_gem_tiling.o \

	  i915_gem_timeline.o \

	  i915_gem_userptr.o \

	  i915_gemfs.o \

	  i915_query.o \

	  i915_request.o \

	  i915_timeline.o \

	  i915_trace_points.o \

	  i915_vma.o \

	  intel_breadcrumbs.o \
@@ -154,7 +158,8 @@ i915-y += dvo_ch7017.o \ 
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o

i915-$(CONFIG_DRM_I915_SELFTEST) += \

	selftests/i915_random.o \

	selftests/i915_selftest.o

	selftests/i915_selftest.o \

	selftests/igt_flush_test.o



# virtual gpu code

i915-y += i915_vgpu.o

drivers/gpu/drm/i915/gvt/cmd_parser.c

+63 −18
Original line number Diff line number Diff line
@@ -813,15 +813,31 @@ static inline bool is_force_nonpriv_mmio(unsigned int offset) 
}



static int force_nonpriv_reg_handler(struct parser_exec_state *s,

				     unsigned int offset, unsigned int index)

		unsigned int offset, unsigned int index, char *cmd)

{

	struct intel_gvt *gvt = s->vgpu->gvt;

	unsigned int data = cmd_val(s, index + 1);

	unsigned int data;

	u32 ring_base;

	u32 nopid;

	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;



	if (!strcmp(cmd, "lri"))

		data = cmd_val(s, index + 1);

	else {

		gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n",

			offset, cmd);

		return -EINVAL;

	}



	if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) {

	ring_base = dev_priv->engine[s->ring_id]->mmio_base;

	nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));



	if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&

			data != nopid) {

		gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",

			offset, data);

		return -EPERM;

		patch_value(s, cmd_ptr(s, index), nopid);

		return 0;

	}

	return 0;

}
@@ -869,7 +885,7 @@ static int cmd_reg_handler(struct parser_exec_state *s, 
		return -EINVAL;



	if (is_force_nonpriv_mmio(offset) &&

		force_nonpriv_reg_handler(s, offset, index))

		force_nonpriv_reg_handler(s, offset, index, cmd))

		return -EPERM;



	if (offset == i915_mmio_reg_offset(DERRMR) ||
@@ -1604,7 +1620,8 @@ static int batch_buffer_needs_scan(struct parser_exec_state *s) 
	if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)

		|| IS_KABYLAKE(gvt->dev_priv)) {

		/* BDW decides privilege based on address space */

		if (cmd_val(s, 0) & (1 << 8))

		if (cmd_val(s, 0) & (1 << 8) &&

			!(s->vgpu->scan_nonprivbb & (1 << s->ring_id)))

			return 0;

	}

	return 1;
@@ -1618,6 +1635,8 @@ static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size) 
	bool bb_end = false;

	struct intel_vgpu *vgpu = s->vgpu;

	u32 cmd;

	struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?

		s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;



	*bb_size = 0;
@@ -1629,18 +1648,22 @@ static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size) 
	cmd = cmd_val(s, 0);

	info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);

	if (info == NULL) {

		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n",

				cmd, get_opcode(cmd, s->ring_id));

		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",

				cmd, get_opcode(cmd, s->ring_id),

				(s->buf_addr_type == PPGTT_BUFFER) ?

				"ppgtt" : "ggtt", s->ring_id, s->workload);

		return -EBADRQC;

	}

	do {

		if (copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm,

		if (copy_gma_to_hva(s->vgpu, mm,

				gma, gma + 4, &cmd) < 0)

			return -EFAULT;

		info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);

		if (info == NULL) {

			gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n",

				cmd, get_opcode(cmd, s->ring_id));

			gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",

				cmd, get_opcode(cmd, s->ring_id),

				(s->buf_addr_type == PPGTT_BUFFER) ?

				"ppgtt" : "ggtt", s->ring_id, s->workload);

			return -EBADRQC;

		}
@@ -1666,6 +1689,9 @@ static int perform_bb_shadow(struct parser_exec_state *s) 
	unsigned long gma = 0;

	unsigned long bb_size;

	int ret = 0;

	struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?

		s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;

	unsigned long gma_start_offset = 0;



	/* get the start gm address of the batch buffer */

	gma = get_gma_bb_from_cmd(s, 1);
@@ -1680,8 +1706,24 @@ static int perform_bb_shadow(struct parser_exec_state *s) 
	if (!bb)

		return -ENOMEM;



	bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;



	/* the gma_start_offset stores the batch buffer's start gma's

	 * offset relative to page boundary. so for non-privileged batch

	 * buffer, the shadowed gem object holds exactly the same page

	 * layout as original gem object. This is for the convience of

	 * replacing the whole non-privilged batch buffer page to this

	 * shadowed one in PPGTT at the same gma address. (this replacing

	 * action is not implemented yet now, but may be necessary in

	 * future).

	 * for prileged batch buffer, we just change start gma address to

	 * that of shadowed page.

	 */

	if (bb->ppgtt)

		gma_start_offset = gma & ~I915_GTT_PAGE_MASK;



	bb->obj = i915_gem_object_create(s->vgpu->gvt->dev_priv,

					 roundup(bb_size, PAGE_SIZE));

			 roundup(bb_size + gma_start_offset, PAGE_SIZE));

	if (IS_ERR(bb->obj)) {

		ret = PTR_ERR(bb->obj);

		goto err_free_bb;
@@ -1702,9 +1744,9 @@ static int perform_bb_shadow(struct parser_exec_state *s) 
		bb->clflush &= ~CLFLUSH_BEFORE;

	}



	ret = copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm,

	ret = copy_gma_to_hva(s->vgpu, mm,

			      gma, gma + bb_size,

			      bb->va);

			      bb->va + gma_start_offset);

	if (ret < 0) {

		gvt_vgpu_err("fail to copy guest ring buffer\n");

		ret = -EFAULT;
@@ -1730,7 +1772,7 @@ static int perform_bb_shadow(struct parser_exec_state *s) 
	 * buffer's gma in pair. After all, we don't want to pin the shadow

	 * buffer here (too early).

	 */

	s->ip_va = bb->va;

	s->ip_va = bb->va + gma_start_offset;

	s->ip_gma = gma;

	return 0;

err_unmap:
@@ -2469,15 +2511,18 @@ static int cmd_parser_exec(struct parser_exec_state *s) 


	info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);

	if (info == NULL) {

		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n",

				cmd, get_opcode(cmd, s->ring_id));

		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",

				cmd, get_opcode(cmd, s->ring_id),

				(s->buf_addr_type == PPGTT_BUFFER) ?

				"ppgtt" : "ggtt", s->ring_id, s->workload);

		return -EBADRQC;

	}



	s->info = info;



	trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va,

			  cmd_length(s), s->buf_type);

			  cmd_length(s), s->buf_type, s->buf_addr_type,

			  s->workload, info->name);



	if (info->handler) {

		ret = info->handler(s);

drivers/gpu/drm/i915/gvt/debugfs.c

+67 −0
Original line number Diff line number Diff line
@@ -124,6 +124,68 @@ static int vgpu_mmio_diff_show(struct seq_file *s, void *unused) 
}

DEFINE_SHOW_ATTRIBUTE(vgpu_mmio_diff);



static int

vgpu_scan_nonprivbb_get(void *data, u64 *val)

{

	struct intel_vgpu *vgpu = (struct intel_vgpu *)data;

	*val = vgpu->scan_nonprivbb;

	return 0;

}



/*

 * set/unset bit engine_id of vgpu->scan_nonprivbb to turn on/off scanning

 * of non-privileged batch buffer. e.g.

 * if vgpu->scan_nonprivbb=3, then it will scan non-privileged batch buffer

 * on engine 0 and 1.

 */

static int

vgpu_scan_nonprivbb_set(void *data, u64 val)

{

	struct intel_vgpu *vgpu = (struct intel_vgpu *)data;

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	enum intel_engine_id id;

	char buf[128], *s;

	int len;



	val &= (1 << I915_NUM_ENGINES) - 1;



	if (vgpu->scan_nonprivbb == val)

		return 0;



	if (!val)

		goto done;



	len = sprintf(buf,

		"gvt: vgpu %d turns on non-privileged batch buffers scanning on Engines:",

		vgpu->id);



	s = buf + len;



	for (id = 0; id < I915_NUM_ENGINES; id++) {

		struct intel_engine_cs *engine;



		engine = dev_priv->engine[id];

		if (engine && (val & (1 << id))) {

			len = snprintf(s, 4, "%d, ", engine->id);

			s += len;

		} else

			val &=  ~(1 << id);

	}



	if (val)

		sprintf(s, "low performance expected.");



	pr_warn("%s\n", buf);



done:

	vgpu->scan_nonprivbb = val;

	return 0;

}



DEFINE_SIMPLE_ATTRIBUTE(vgpu_scan_nonprivbb_fops,

			vgpu_scan_nonprivbb_get, vgpu_scan_nonprivbb_set,

			"0x%llx\n");



/**

 * intel_gvt_debugfs_add_vgpu - register debugfs entries for a vGPU

 * @vgpu: a vGPU
@@ -151,6 +213,11 @@ int intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu) 
	if (!ent)

		return -ENOMEM;



	ent = debugfs_create_file("scan_nonprivbb", 0644, vgpu->debugfs,

				 vgpu, &vgpu_scan_nonprivbb_fops);

	if (!ent)

		return -ENOMEM;



	return 0;

}

drivers/gpu/drm/i915/gvt/gvt.h

+1 −1
Original line number Diff line number Diff line
@@ -99,7 +99,6 @@ struct intel_vgpu_fence { 
struct intel_vgpu_mmio {

	void *vreg;

	void *sreg;

	bool disable_warn_untrack;

};



#define INTEL_GVT_MAX_BAR_NUM 4
@@ -226,6 +225,7 @@ struct intel_vgpu { 


	struct completion vblank_done;



	u32 scan_nonprivbb;

};



/* validating GM healthy status*/