drm/msm/dsi-staging: reset clk enable select bit after FIFO resync

For each clock state change on DSI link clocks, toggling
of resync fifo register is needed. During this operation
clk_en_sel bit should be set high per latest hardware
specification. After resync fifo is toggled, clk_en_sel
bit has to be unset.

Change-Id: Ie2bac6a12aac7d0f81a819d5d20964b521ec0307
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>