ARM: tegra: Remove pre-pinctrl pinmux driver (b7449d95) · Commits · e / devices / android_kernel_xiaomi_nabu

arch/arm/mach-tegra/Makefile

+0 −3

Original line number	Original line	Diff line number	Diff line
	@@ -5,7 +5,6 @@ obj-y += io.o
	obj-y += irq.o		obj-y += irq.o
	obj-y += clock.o		obj-y += clock.o
	obj-y += timer.o		obj-y += timer.o
	obj-y += pinmux.o
	obj-y += fuse.o		obj-y += fuse.o
	obj-y += pmc.o		obj-y += pmc.o
	obj-y += flowctrl.o		obj-y += flowctrl.o
	@@ -14,8 +13,6 @@ obj-$(CONFIG_CPU_IDLE) += sleep.o
	obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o		obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
	obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o		obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
	obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o		obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
	obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o
	obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
	obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o		obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
	obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o		obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
	obj-$(CONFIG_SMP) += platsmp.o headsmp.o		obj-$(CONFIG_SMP) += platsmp.o headsmp.o

arch/arm/mach-tegra/include/mach/pinmux-tegra20.h

deleted100644 → 0

+0 −184

Original line number	Original line	Diff line number	Diff line
	/*
	* linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
	*
	* Copyright (C) 2010 Google, Inc.
	*
	* This software is licensed under the terms of the GNU General Public
	* License version 2, as published by the Free Software Foundation, and
	* may be copied, distributed, and modified under those terms.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	*/

	#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
	#define __MACH_TEGRA_PINMUX_TEGRA20_H

	enum tegra_pingroup {
	TEGRA_PINGROUP_ATA = 0,
	TEGRA_PINGROUP_ATB,
	TEGRA_PINGROUP_ATC,
	TEGRA_PINGROUP_ATD,
	TEGRA_PINGROUP_ATE,
	TEGRA_PINGROUP_CDEV1,
	TEGRA_PINGROUP_CDEV2,
	TEGRA_PINGROUP_CRTP,
	TEGRA_PINGROUP_CSUS,
	TEGRA_PINGROUP_DAP1,
	TEGRA_PINGROUP_DAP2,
	TEGRA_PINGROUP_DAP3,
	TEGRA_PINGROUP_DAP4,
	TEGRA_PINGROUP_DDC,
	TEGRA_PINGROUP_DTA,
	TEGRA_PINGROUP_DTB,
	TEGRA_PINGROUP_DTC,
	TEGRA_PINGROUP_DTD,
	TEGRA_PINGROUP_DTE,
	TEGRA_PINGROUP_DTF,
	TEGRA_PINGROUP_GMA,
	TEGRA_PINGROUP_GMB,
	TEGRA_PINGROUP_GMC,
	TEGRA_PINGROUP_GMD,
	TEGRA_PINGROUP_GME,
	TEGRA_PINGROUP_GPU,
	TEGRA_PINGROUP_GPU7,
	TEGRA_PINGROUP_GPV,
	TEGRA_PINGROUP_HDINT,
	TEGRA_PINGROUP_I2CP,
	TEGRA_PINGROUP_IRRX,
	TEGRA_PINGROUP_IRTX,
	TEGRA_PINGROUP_KBCA,
	TEGRA_PINGROUP_KBCB,
	TEGRA_PINGROUP_KBCC,
	TEGRA_PINGROUP_KBCD,
	TEGRA_PINGROUP_KBCE,
	TEGRA_PINGROUP_KBCF,
	TEGRA_PINGROUP_LCSN,
	TEGRA_PINGROUP_LD0,
	TEGRA_PINGROUP_LD1,
	TEGRA_PINGROUP_LD10,
	TEGRA_PINGROUP_LD11,
	TEGRA_PINGROUP_LD12,
	TEGRA_PINGROUP_LD13,
	TEGRA_PINGROUP_LD14,
	TEGRA_PINGROUP_LD15,
	TEGRA_PINGROUP_LD16,
	TEGRA_PINGROUP_LD17,
	TEGRA_PINGROUP_LD2,
	TEGRA_PINGROUP_LD3,
	TEGRA_PINGROUP_LD4,
	TEGRA_PINGROUP_LD5,
	TEGRA_PINGROUP_LD6,
	TEGRA_PINGROUP_LD7,
	TEGRA_PINGROUP_LD8,
	TEGRA_PINGROUP_LD9,
	TEGRA_PINGROUP_LDC,
	TEGRA_PINGROUP_LDI,
	TEGRA_PINGROUP_LHP0,
	TEGRA_PINGROUP_LHP1,
	TEGRA_PINGROUP_LHP2,
	TEGRA_PINGROUP_LHS,
	TEGRA_PINGROUP_LM0,
	TEGRA_PINGROUP_LM1,
	TEGRA_PINGROUP_LPP,
	TEGRA_PINGROUP_LPW0,
	TEGRA_PINGROUP_LPW1,
	TEGRA_PINGROUP_LPW2,
	TEGRA_PINGROUP_LSC0,
	TEGRA_PINGROUP_LSC1,
	TEGRA_PINGROUP_LSCK,
	TEGRA_PINGROUP_LSDA,
	TEGRA_PINGROUP_LSDI,
	TEGRA_PINGROUP_LSPI,
	TEGRA_PINGROUP_LVP0,
	TEGRA_PINGROUP_LVP1,
	TEGRA_PINGROUP_LVS,
	TEGRA_PINGROUP_OWC,
	TEGRA_PINGROUP_PMC,
	TEGRA_PINGROUP_PTA,
	TEGRA_PINGROUP_RM,
	TEGRA_PINGROUP_SDB,
	TEGRA_PINGROUP_SDC,
	TEGRA_PINGROUP_SDD,
	TEGRA_PINGROUP_SDIO1,
	TEGRA_PINGROUP_SLXA,
	TEGRA_PINGROUP_SLXC,
	TEGRA_PINGROUP_SLXD,
	TEGRA_PINGROUP_SLXK,
	TEGRA_PINGROUP_SPDI,
	TEGRA_PINGROUP_SPDO,
	TEGRA_PINGROUP_SPIA,
	TEGRA_PINGROUP_SPIB,
	TEGRA_PINGROUP_SPIC,
	TEGRA_PINGROUP_SPID,
	TEGRA_PINGROUP_SPIE,
	TEGRA_PINGROUP_SPIF,
	TEGRA_PINGROUP_SPIG,
	TEGRA_PINGROUP_SPIH,
	TEGRA_PINGROUP_UAA,
	TEGRA_PINGROUP_UAB,
	TEGRA_PINGROUP_UAC,
	TEGRA_PINGROUP_UAD,
	TEGRA_PINGROUP_UCA,
	TEGRA_PINGROUP_UCB,
	TEGRA_PINGROUP_UDA,
	/* these pin groups only have pullup and pull down control */
	TEGRA_PINGROUP_CK32,
	TEGRA_PINGROUP_DDRC,
	TEGRA_PINGROUP_PMCA,
	TEGRA_PINGROUP_PMCB,
	TEGRA_PINGROUP_PMCC,
	TEGRA_PINGROUP_PMCD,
	TEGRA_PINGROUP_PMCE,
	TEGRA_PINGROUP_XM2C,
	TEGRA_PINGROUP_XM2D,
	TEGRA_MAX_PINGROUP,
	};

	enum tegra_drive_pingroup {
	TEGRA_DRIVE_PINGROUP_AO1 = 0,
	TEGRA_DRIVE_PINGROUP_AO2,
	TEGRA_DRIVE_PINGROUP_AT1,
	TEGRA_DRIVE_PINGROUP_AT2,
	TEGRA_DRIVE_PINGROUP_CDEV1,
	TEGRA_DRIVE_PINGROUP_CDEV2,
	TEGRA_DRIVE_PINGROUP_CSUS,
	TEGRA_DRIVE_PINGROUP_DAP1,
	TEGRA_DRIVE_PINGROUP_DAP2,
	TEGRA_DRIVE_PINGROUP_DAP3,
	TEGRA_DRIVE_PINGROUP_DAP4,
	TEGRA_DRIVE_PINGROUP_DBG,
	TEGRA_DRIVE_PINGROUP_LCD1,
	TEGRA_DRIVE_PINGROUP_LCD2,
	TEGRA_DRIVE_PINGROUP_SDMMC2,
	TEGRA_DRIVE_PINGROUP_SDMMC3,
	TEGRA_DRIVE_PINGROUP_SPI,
	TEGRA_DRIVE_PINGROUP_UAA,
	TEGRA_DRIVE_PINGROUP_UAB,
	TEGRA_DRIVE_PINGROUP_UART2,
	TEGRA_DRIVE_PINGROUP_UART3,
	TEGRA_DRIVE_PINGROUP_VI1,
	TEGRA_DRIVE_PINGROUP_VI2,
	TEGRA_DRIVE_PINGROUP_XM2A,
	TEGRA_DRIVE_PINGROUP_XM2C,
	TEGRA_DRIVE_PINGROUP_XM2D,
	TEGRA_DRIVE_PINGROUP_XM2CLK,
	TEGRA_DRIVE_PINGROUP_MEMCOMP,
	TEGRA_DRIVE_PINGROUP_SDIO1,
	TEGRA_DRIVE_PINGROUP_CRT,
	TEGRA_DRIVE_PINGROUP_DDC,
	TEGRA_DRIVE_PINGROUP_GMA,
	TEGRA_DRIVE_PINGROUP_GMB,
	TEGRA_DRIVE_PINGROUP_GMC,
	TEGRA_DRIVE_PINGROUP_GMD,
	TEGRA_DRIVE_PINGROUP_GME,
	TEGRA_DRIVE_PINGROUP_OWR,
	TEGRA_DRIVE_PINGROUP_UAD,
	TEGRA_MAX_DRIVE_PINGROUP,
	};

	#endif

arch/arm/mach-tegra/include/mach/pinmux-tegra30.h

deleted100644 → 0

+0 −320

Original line number	Original line	Diff line number	Diff line
	/*
	* linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
	*
	* Copyright (C) 2010 Google, Inc.
	* Copyright (C) 2010,2011 Nvidia, Inc.
	*
	* This software is licensed under the terms of the GNU General Public
	* License version 2, as published by the Free Software Foundation, and
	* may be copied, distributed, and modified under those terms.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	*/

	#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
	#define __MACH_TEGRA_PINMUX_TEGRA30_H

	enum tegra_pingroup {
	TEGRA_PINGROUP_ULPI_DATA0 = 0,
	TEGRA_PINGROUP_ULPI_DATA1,
	TEGRA_PINGROUP_ULPI_DATA2,
	TEGRA_PINGROUP_ULPI_DATA3,
	TEGRA_PINGROUP_ULPI_DATA4,
	TEGRA_PINGROUP_ULPI_DATA5,
	TEGRA_PINGROUP_ULPI_DATA6,
	TEGRA_PINGROUP_ULPI_DATA7,
	TEGRA_PINGROUP_ULPI_CLK,
	TEGRA_PINGROUP_ULPI_DIR,
	TEGRA_PINGROUP_ULPI_NXT,
	TEGRA_PINGROUP_ULPI_STP,
	TEGRA_PINGROUP_DAP3_FS,
	TEGRA_PINGROUP_DAP3_DIN,
	TEGRA_PINGROUP_DAP3_DOUT,
	TEGRA_PINGROUP_DAP3_SCLK,
	TEGRA_PINGROUP_GPIO_PV0,
	TEGRA_PINGROUP_GPIO_PV1,
	TEGRA_PINGROUP_SDMMC1_CLK,
	TEGRA_PINGROUP_SDMMC1_CMD,
	TEGRA_PINGROUP_SDMMC1_DAT3,
	TEGRA_PINGROUP_SDMMC1_DAT2,
	TEGRA_PINGROUP_SDMMC1_DAT1,
	TEGRA_PINGROUP_SDMMC1_DAT0,
	TEGRA_PINGROUP_GPIO_PV2,
	TEGRA_PINGROUP_GPIO_PV3,
	TEGRA_PINGROUP_CLK2_OUT,
	TEGRA_PINGROUP_CLK2_REQ,
	TEGRA_PINGROUP_LCD_PWR1,
	TEGRA_PINGROUP_LCD_PWR2,
	TEGRA_PINGROUP_LCD_SDIN,
	TEGRA_PINGROUP_LCD_SDOUT,
	TEGRA_PINGROUP_LCD_WR_N,
	TEGRA_PINGROUP_LCD_CS0_N,
	TEGRA_PINGROUP_LCD_DC0,
	TEGRA_PINGROUP_LCD_SCK,
	TEGRA_PINGROUP_LCD_PWR0,
	TEGRA_PINGROUP_LCD_PCLK,
	TEGRA_PINGROUP_LCD_DE,
	TEGRA_PINGROUP_LCD_HSYNC,
	TEGRA_PINGROUP_LCD_VSYNC,
	TEGRA_PINGROUP_LCD_D0,
	TEGRA_PINGROUP_LCD_D1,
	TEGRA_PINGROUP_LCD_D2,
	TEGRA_PINGROUP_LCD_D3,
	TEGRA_PINGROUP_LCD_D4,
	TEGRA_PINGROUP_LCD_D5,
	TEGRA_PINGROUP_LCD_D6,
	TEGRA_PINGROUP_LCD_D7,
	TEGRA_PINGROUP_LCD_D8,
	TEGRA_PINGROUP_LCD_D9,
	TEGRA_PINGROUP_LCD_D10,
	TEGRA_PINGROUP_LCD_D11,
	TEGRA_PINGROUP_LCD_D12,
	TEGRA_PINGROUP_LCD_D13,
	TEGRA_PINGROUP_LCD_D14,
	TEGRA_PINGROUP_LCD_D15,
	TEGRA_PINGROUP_LCD_D16,
	TEGRA_PINGROUP_LCD_D17,
	TEGRA_PINGROUP_LCD_D18,
	TEGRA_PINGROUP_LCD_D19,
	TEGRA_PINGROUP_LCD_D20,
	TEGRA_PINGROUP_LCD_D21,
	TEGRA_PINGROUP_LCD_D22,
	TEGRA_PINGROUP_LCD_D23,
	TEGRA_PINGROUP_LCD_CS1_N,
	TEGRA_PINGROUP_LCD_M1,
	TEGRA_PINGROUP_LCD_DC1,
	TEGRA_PINGROUP_HDMI_INT,
	TEGRA_PINGROUP_DDC_SCL,
	TEGRA_PINGROUP_DDC_SDA,
	TEGRA_PINGROUP_CRT_HSYNC,
	TEGRA_PINGROUP_CRT_VSYNC,
	TEGRA_PINGROUP_VI_D0,
	TEGRA_PINGROUP_VI_D1,
	TEGRA_PINGROUP_VI_D2,
	TEGRA_PINGROUP_VI_D3,
	TEGRA_PINGROUP_VI_D4,
	TEGRA_PINGROUP_VI_D5,
	TEGRA_PINGROUP_VI_D6,
	TEGRA_PINGROUP_VI_D7,
	TEGRA_PINGROUP_VI_D8,
	TEGRA_PINGROUP_VI_D9,
	TEGRA_PINGROUP_VI_D10,
	TEGRA_PINGROUP_VI_D11,
	TEGRA_PINGROUP_VI_PCLK,
	TEGRA_PINGROUP_VI_MCLK,
	TEGRA_PINGROUP_VI_VSYNC,
	TEGRA_PINGROUP_VI_HSYNC,
	TEGRA_PINGROUP_UART2_RXD,
	TEGRA_PINGROUP_UART2_TXD,
	TEGRA_PINGROUP_UART2_RTS_N,
	TEGRA_PINGROUP_UART2_CTS_N,
	TEGRA_PINGROUP_UART3_TXD,
	TEGRA_PINGROUP_UART3_RXD,
	TEGRA_PINGROUP_UART3_CTS_N,
	TEGRA_PINGROUP_UART3_RTS_N,
	TEGRA_PINGROUP_GPIO_PU0,
	TEGRA_PINGROUP_GPIO_PU1,
	TEGRA_PINGROUP_GPIO_PU2,
	TEGRA_PINGROUP_GPIO_PU3,
	TEGRA_PINGROUP_GPIO_PU4,
	TEGRA_PINGROUP_GPIO_PU5,
	TEGRA_PINGROUP_GPIO_PU6,
	TEGRA_PINGROUP_GEN1_I2C_SDA,
	TEGRA_PINGROUP_GEN1_I2C_SCL,
	TEGRA_PINGROUP_DAP4_FS,
	TEGRA_PINGROUP_DAP4_DIN,
	TEGRA_PINGROUP_DAP4_DOUT,
	TEGRA_PINGROUP_DAP4_SCLK,
	TEGRA_PINGROUP_CLK3_OUT,
	TEGRA_PINGROUP_CLK3_REQ,
	TEGRA_PINGROUP_GMI_WP_N,
	TEGRA_PINGROUP_GMI_IORDY,
	TEGRA_PINGROUP_GMI_WAIT,
	TEGRA_PINGROUP_GMI_ADV_N,
	TEGRA_PINGROUP_GMI_CLK,
	TEGRA_PINGROUP_GMI_CS0_N,
	TEGRA_PINGROUP_GMI_CS1_N,
	TEGRA_PINGROUP_GMI_CS2_N,
	TEGRA_PINGROUP_GMI_CS3_N,
	TEGRA_PINGROUP_GMI_CS4_N,
	TEGRA_PINGROUP_GMI_CS6_N,
	TEGRA_PINGROUP_GMI_CS7_N,
	TEGRA_PINGROUP_GMI_AD0,
	TEGRA_PINGROUP_GMI_AD1,
	TEGRA_PINGROUP_GMI_AD2,
	TEGRA_PINGROUP_GMI_AD3,
	TEGRA_PINGROUP_GMI_AD4,
	TEGRA_PINGROUP_GMI_AD5,
	TEGRA_PINGROUP_GMI_AD6,
	TEGRA_PINGROUP_GMI_AD7,
	TEGRA_PINGROUP_GMI_AD8,
	TEGRA_PINGROUP_GMI_AD9,
	TEGRA_PINGROUP_GMI_AD10,
	TEGRA_PINGROUP_GMI_AD11,
	TEGRA_PINGROUP_GMI_AD12,
	TEGRA_PINGROUP_GMI_AD13,
	TEGRA_PINGROUP_GMI_AD14,
	TEGRA_PINGROUP_GMI_AD15,
	TEGRA_PINGROUP_GMI_A16,
	TEGRA_PINGROUP_GMI_A17,
	TEGRA_PINGROUP_GMI_A18,
	TEGRA_PINGROUP_GMI_A19,
	TEGRA_PINGROUP_GMI_WR_N,
	TEGRA_PINGROUP_GMI_OE_N,
	TEGRA_PINGROUP_GMI_DQS,
	TEGRA_PINGROUP_GMI_RST_N,
	TEGRA_PINGROUP_GEN2_I2C_SCL,
	TEGRA_PINGROUP_GEN2_I2C_SDA,
	TEGRA_PINGROUP_SDMMC4_CLK,
	TEGRA_PINGROUP_SDMMC4_CMD,
	TEGRA_PINGROUP_SDMMC4_DAT0,
	TEGRA_PINGROUP_SDMMC4_DAT1,
	TEGRA_PINGROUP_SDMMC4_DAT2,
	TEGRA_PINGROUP_SDMMC4_DAT3,
	TEGRA_PINGROUP_SDMMC4_DAT4,
	TEGRA_PINGROUP_SDMMC4_DAT5,
	TEGRA_PINGROUP_SDMMC4_DAT6,
	TEGRA_PINGROUP_SDMMC4_DAT7,
	TEGRA_PINGROUP_SDMMC4_RST_N,
	TEGRA_PINGROUP_CAM_MCLK,
	TEGRA_PINGROUP_GPIO_PCC1,
	TEGRA_PINGROUP_GPIO_PBB0,
	TEGRA_PINGROUP_CAM_I2C_SCL,
	TEGRA_PINGROUP_CAM_I2C_SDA,
	TEGRA_PINGROUP_GPIO_PBB3,
	TEGRA_PINGROUP_GPIO_PBB4,
	TEGRA_PINGROUP_GPIO_PBB5,
	TEGRA_PINGROUP_GPIO_PBB6,
	TEGRA_PINGROUP_GPIO_PBB7,
	TEGRA_PINGROUP_GPIO_PCC2,
	TEGRA_PINGROUP_JTAG_RTCK,
	TEGRA_PINGROUP_PWR_I2C_SCL,
	TEGRA_PINGROUP_PWR_I2C_SDA,
	TEGRA_PINGROUP_KB_ROW0,
	TEGRA_PINGROUP_KB_ROW1,
	TEGRA_PINGROUP_KB_ROW2,
	TEGRA_PINGROUP_KB_ROW3,
	TEGRA_PINGROUP_KB_ROW4,
	TEGRA_PINGROUP_KB_ROW5,
	TEGRA_PINGROUP_KB_ROW6,
	TEGRA_PINGROUP_KB_ROW7,
	TEGRA_PINGROUP_KB_ROW8,
	TEGRA_PINGROUP_KB_ROW9,
	TEGRA_PINGROUP_KB_ROW10,
	TEGRA_PINGROUP_KB_ROW11,
	TEGRA_PINGROUP_KB_ROW12,
	TEGRA_PINGROUP_KB_ROW13,
	TEGRA_PINGROUP_KB_ROW14,
	TEGRA_PINGROUP_KB_ROW15,
	TEGRA_PINGROUP_KB_COL0,
	TEGRA_PINGROUP_KB_COL1,
	TEGRA_PINGROUP_KB_COL2,
	TEGRA_PINGROUP_KB_COL3,
	TEGRA_PINGROUP_KB_COL4,
	TEGRA_PINGROUP_KB_COL5,
	TEGRA_PINGROUP_KB_COL6,
	TEGRA_PINGROUP_KB_COL7,
	TEGRA_PINGROUP_CLK_32K_OUT,
	TEGRA_PINGROUP_SYS_CLK_REQ,
	TEGRA_PINGROUP_CORE_PWR_REQ,
	TEGRA_PINGROUP_CPU_PWR_REQ,
	TEGRA_PINGROUP_PWR_INT_N,
	TEGRA_PINGROUP_CLK_32K_IN,
	TEGRA_PINGROUP_OWR,
	TEGRA_PINGROUP_DAP1_FS,
	TEGRA_PINGROUP_DAP1_DIN,
	TEGRA_PINGROUP_DAP1_DOUT,
	TEGRA_PINGROUP_DAP1_SCLK,
	TEGRA_PINGROUP_CLK1_REQ,
	TEGRA_PINGROUP_CLK1_OUT,
	TEGRA_PINGROUP_SPDIF_IN,
	TEGRA_PINGROUP_SPDIF_OUT,
	TEGRA_PINGROUP_DAP2_FS,
	TEGRA_PINGROUP_DAP2_DIN,
	TEGRA_PINGROUP_DAP2_DOUT,
	TEGRA_PINGROUP_DAP2_SCLK,
	TEGRA_PINGROUP_SPI2_MOSI,
	TEGRA_PINGROUP_SPI2_MISO,
	TEGRA_PINGROUP_SPI2_CS0_N,
	TEGRA_PINGROUP_SPI2_SCK,
	TEGRA_PINGROUP_SPI1_MOSI,
	TEGRA_PINGROUP_SPI1_SCK,
	TEGRA_PINGROUP_SPI1_CS0_N,
	TEGRA_PINGROUP_SPI1_MISO,
	TEGRA_PINGROUP_SPI2_CS1_N,
	TEGRA_PINGROUP_SPI2_CS2_N,
	TEGRA_PINGROUP_SDMMC3_CLK,
	TEGRA_PINGROUP_SDMMC3_CMD,
	TEGRA_PINGROUP_SDMMC3_DAT0,
	TEGRA_PINGROUP_SDMMC3_DAT1,
	TEGRA_PINGROUP_SDMMC3_DAT2,
	TEGRA_PINGROUP_SDMMC3_DAT3,
	TEGRA_PINGROUP_SDMMC3_DAT4,
	TEGRA_PINGROUP_SDMMC3_DAT5,
	TEGRA_PINGROUP_SDMMC3_DAT6,
	TEGRA_PINGROUP_SDMMC3_DAT7,
	TEGRA_PINGROUP_PEX_L0_PRSNT_N,
	TEGRA_PINGROUP_PEX_L0_RST_N,
	TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
	TEGRA_PINGROUP_PEX_WAKE_N,
	TEGRA_PINGROUP_PEX_L1_PRSNT_N,
	TEGRA_PINGROUP_PEX_L1_RST_N,
	TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
	TEGRA_PINGROUP_PEX_L2_PRSNT_N,
	TEGRA_PINGROUP_PEX_L2_RST_N,
	TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
	TEGRA_PINGROUP_HDMI_CEC,
	TEGRA_MAX_PINGROUP,
	};

	enum tegra_drive_pingroup {
	TEGRA_DRIVE_PINGROUP_AO1 = 0,
	TEGRA_DRIVE_PINGROUP_AO2,
	TEGRA_DRIVE_PINGROUP_AT1,
	TEGRA_DRIVE_PINGROUP_AT2,
	TEGRA_DRIVE_PINGROUP_AT3,
	TEGRA_DRIVE_PINGROUP_AT4,
	TEGRA_DRIVE_PINGROUP_AT5,
	TEGRA_DRIVE_PINGROUP_CDEV1,
	TEGRA_DRIVE_PINGROUP_CDEV2,
	TEGRA_DRIVE_PINGROUP_CSUS,
	TEGRA_DRIVE_PINGROUP_DAP1,
	TEGRA_DRIVE_PINGROUP_DAP2,
	TEGRA_DRIVE_PINGROUP_DAP3,
	TEGRA_DRIVE_PINGROUP_DAP4,
	TEGRA_DRIVE_PINGROUP_DBG,
	TEGRA_DRIVE_PINGROUP_LCD1,
	TEGRA_DRIVE_PINGROUP_LCD2,
	TEGRA_DRIVE_PINGROUP_SDIO2,
	TEGRA_DRIVE_PINGROUP_SDIO3,
	TEGRA_DRIVE_PINGROUP_SPI,
	TEGRA_DRIVE_PINGROUP_UAA,
	TEGRA_DRIVE_PINGROUP_UAB,
	TEGRA_DRIVE_PINGROUP_UART2,
	TEGRA_DRIVE_PINGROUP_UART3,
	TEGRA_DRIVE_PINGROUP_VI1,
	TEGRA_DRIVE_PINGROUP_SDIO1,
	TEGRA_DRIVE_PINGROUP_CRT,
	TEGRA_DRIVE_PINGROUP_DDC,
	TEGRA_DRIVE_PINGROUP_GMA,
	TEGRA_DRIVE_PINGROUP_GMB,
	TEGRA_DRIVE_PINGROUP_GMC,
	TEGRA_DRIVE_PINGROUP_GMD,
	TEGRA_DRIVE_PINGROUP_GME,
	TEGRA_DRIVE_PINGROUP_GMF,
	TEGRA_DRIVE_PINGROUP_GMG,
	TEGRA_DRIVE_PINGROUP_GMH,
	TEGRA_DRIVE_PINGROUP_OWR,
	TEGRA_DRIVE_PINGROUP_UAD,
	TEGRA_DRIVE_PINGROUP_GPV,
	TEGRA_DRIVE_PINGROUP_DEV3,
	TEGRA_DRIVE_PINGROUP_CEC,
	TEGRA_MAX_DRIVE_PINGROUP,
	};

	#endif

arch/arm/mach-tegra/include/mach/pinmux.h

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Original line number	Original line	Diff line number	Diff line
	/*
	* linux/arch/arm/mach-tegra/include/mach/pinmux.h
	*
	* Copyright (C) 2010 Google, Inc.
	* Copyright (C) 2010,2011 Nvidia, Inc.
	*
	* This software is licensed under the terms of the GNU General Public
	* License version 2, as published by the Free Software Foundation, and
	* may be copied, distributed, and modified under those terms.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	*/

	#ifndef __MACH_TEGRA_PINMUX_H
	#define __MACH_TEGRA_PINMUX_H

	enum tegra_mux_func {
	TEGRA_MUX_RSVD = 0x8000,
	TEGRA_MUX_RSVD1 = 0x8000,
	TEGRA_MUX_RSVD2 = 0x8001,
	TEGRA_MUX_RSVD3 = 0x8002,
	TEGRA_MUX_RSVD4 = 0x8003,
	TEGRA_MUX_INVALID = 0x4000,
	TEGRA_MUX_NONE = -1,
	TEGRA_MUX_AHB_CLK,
	TEGRA_MUX_APB_CLK,
	TEGRA_MUX_AUDIO_SYNC,
	TEGRA_MUX_CRT,
	TEGRA_MUX_DAP1,
	TEGRA_MUX_DAP2,
	TEGRA_MUX_DAP3,
	TEGRA_MUX_DAP4,
	TEGRA_MUX_DAP5,
	TEGRA_MUX_DISPLAYA,
	TEGRA_MUX_DISPLAYB,
	TEGRA_MUX_EMC_TEST0_DLL,
	TEGRA_MUX_EMC_TEST1_DLL,
	TEGRA_MUX_GMI,
	TEGRA_MUX_GMI_INT,
	TEGRA_MUX_HDMI,
	TEGRA_MUX_I2C,
	TEGRA_MUX_I2C2,
	TEGRA_MUX_I2C3,
	TEGRA_MUX_IDE,
	TEGRA_MUX_IRDA,
	TEGRA_MUX_KBC,
	TEGRA_MUX_MIO,
	TEGRA_MUX_MIPI_HS,
	TEGRA_MUX_NAND,
	TEGRA_MUX_OSC,
	TEGRA_MUX_OWR,
	TEGRA_MUX_PCIE,
	TEGRA_MUX_PLLA_OUT,
	TEGRA_MUX_PLLC_OUT1,
	TEGRA_MUX_PLLM_OUT1,
	TEGRA_MUX_PLLP_OUT2,
	TEGRA_MUX_PLLP_OUT3,
	TEGRA_MUX_PLLP_OUT4,
	TEGRA_MUX_PWM,
	TEGRA_MUX_PWR_INTR,
	TEGRA_MUX_PWR_ON,
	TEGRA_MUX_RTCK,
	TEGRA_MUX_SDIO1,
	TEGRA_MUX_SDIO2,
	TEGRA_MUX_SDIO3,
	TEGRA_MUX_SDIO4,
	TEGRA_MUX_SFLASH,
	TEGRA_MUX_SPDIF,
	TEGRA_MUX_SPI1,
	TEGRA_MUX_SPI2,
	TEGRA_MUX_SPI2_ALT,
	TEGRA_MUX_SPI3,
	TEGRA_MUX_SPI4,
	TEGRA_MUX_TRACE,
	TEGRA_MUX_TWC,
	TEGRA_MUX_UARTA,
	TEGRA_MUX_UARTB,
	TEGRA_MUX_UARTC,
	TEGRA_MUX_UARTD,
	TEGRA_MUX_UARTE,
	TEGRA_MUX_ULPI,
	TEGRA_MUX_VI,
	TEGRA_MUX_VI_SENSOR_CLK,
	TEGRA_MUX_XIO,
	TEGRA_MUX_BLINK,
	TEGRA_MUX_CEC,
	TEGRA_MUX_CLK12,
	TEGRA_MUX_DAP,
	TEGRA_MUX_DAPSDMMC2,
	TEGRA_MUX_DDR,
	TEGRA_MUX_DEV3,
	TEGRA_MUX_DTV,
	TEGRA_MUX_VI_ALT1,
	TEGRA_MUX_VI_ALT2,
	TEGRA_MUX_VI_ALT3,
	TEGRA_MUX_EMC_DLL,
	TEGRA_MUX_EXTPERIPH1,
	TEGRA_MUX_EXTPERIPH2,
	TEGRA_MUX_EXTPERIPH3,
	TEGRA_MUX_GMI_ALT,
	TEGRA_MUX_HDA,
	TEGRA_MUX_HSI,
	TEGRA_MUX_I2C4,
	TEGRA_MUX_I2C5,
	TEGRA_MUX_I2CPWR,
	TEGRA_MUX_I2S0,
	TEGRA_MUX_I2S1,
	TEGRA_MUX_I2S2,
	TEGRA_MUX_I2S3,
	TEGRA_MUX_I2S4,
	TEGRA_MUX_NAND_ALT,
	TEGRA_MUX_POPSDIO4,
	TEGRA_MUX_POPSDMMC4,
	TEGRA_MUX_PWM0,
	TEGRA_MUX_PWM1,
	TEGRA_MUX_PWM2,
	TEGRA_MUX_PWM3,
	TEGRA_MUX_SATA,
	TEGRA_MUX_SPI5,
	TEGRA_MUX_SPI6,
	TEGRA_MUX_SYSCLK,
	TEGRA_MUX_VGP1,
	TEGRA_MUX_VGP2,
	TEGRA_MUX_VGP3,
	TEGRA_MUX_VGP4,
	TEGRA_MUX_VGP5,
	TEGRA_MUX_VGP6,
	TEGRA_MUX_SAFE,
	TEGRA_MAX_MUX,
	};

	enum tegra_pullupdown {
	TEGRA_PUPD_NORMAL = 0,
	TEGRA_PUPD_PULL_DOWN,
	TEGRA_PUPD_PULL_UP,
	};

	enum tegra_tristate {
	TEGRA_TRI_NORMAL = 0,
	TEGRA_TRI_TRISTATE = 1,
	};

	enum tegra_pin_io {
	TEGRA_PIN_OUTPUT = 0,
	TEGRA_PIN_INPUT = 1,
	};

	enum tegra_vddio {
	TEGRA_VDDIO_BB = 0,
	TEGRA_VDDIO_LCD,
	TEGRA_VDDIO_VI,
	TEGRA_VDDIO_UART,
	TEGRA_VDDIO_DDR,
	TEGRA_VDDIO_NAND,
	TEGRA_VDDIO_SYS,
	TEGRA_VDDIO_AUDIO,
	TEGRA_VDDIO_SD,
	TEGRA_VDDIO_CAM,
	TEGRA_VDDIO_GMI,
	TEGRA_VDDIO_PEXCTL,
	TEGRA_VDDIO_SDMMC1,
	TEGRA_VDDIO_SDMMC3,
	TEGRA_VDDIO_SDMMC4,
	};

	struct tegra_pingroup_config {
	int pingroup;
	enum tegra_mux_func func;
	enum tegra_pullupdown pupd;
	enum tegra_tristate tristate;
	};

	enum tegra_slew {
	TEGRA_SLEW_FASTEST = 0,
	TEGRA_SLEW_FAST,
	TEGRA_SLEW_SLOW,
	TEGRA_SLEW_SLOWEST,
	TEGRA_MAX_SLEW,
	};

	enum tegra_pull_strength {
	TEGRA_PULL_0 = 0,
	TEGRA_PULL_1,
	TEGRA_PULL_2,
	TEGRA_PULL_3,
	TEGRA_PULL_4,
	TEGRA_PULL_5,
	TEGRA_PULL_6,
	TEGRA_PULL_7,
	TEGRA_PULL_8,
	TEGRA_PULL_9,
	TEGRA_PULL_10,
	TEGRA_PULL_11,
	TEGRA_PULL_12,
	TEGRA_PULL_13,
	TEGRA_PULL_14,
	TEGRA_PULL_15,
	TEGRA_PULL_16,
	TEGRA_PULL_17,
	TEGRA_PULL_18,
	TEGRA_PULL_19,
	TEGRA_PULL_20,
	TEGRA_PULL_21,
	TEGRA_PULL_22,
	TEGRA_PULL_23,
	TEGRA_PULL_24,
	TEGRA_PULL_25,
	TEGRA_PULL_26,
	TEGRA_PULL_27,
	TEGRA_PULL_28,
	TEGRA_PULL_29,
	TEGRA_PULL_30,
	TEGRA_PULL_31,
	TEGRA_MAX_PULL,
	};

	enum tegra_drive {
	TEGRA_DRIVE_DIV_8 = 0,
	TEGRA_DRIVE_DIV_4,
	TEGRA_DRIVE_DIV_2,
	TEGRA_DRIVE_DIV_1,
	TEGRA_MAX_DRIVE,
	};

	enum tegra_hsm {
	TEGRA_HSM_DISABLE = 0,
	TEGRA_HSM_ENABLE,
	};

	enum tegra_schmitt {
	TEGRA_SCHMITT_DISABLE = 0,
	TEGRA_SCHMITT_ENABLE,
	};

	struct tegra_drive_pingroup_config {
	int pingroup;
	enum tegra_hsm hsm;
	enum tegra_schmitt schmitt;
	enum tegra_drive drive;
	enum tegra_pull_strength pull_down;
	enum tegra_pull_strength pull_up;
	enum tegra_slew slew_rising;
	enum tegra_slew slew_falling;
	};

	struct tegra_drive_pingroup_desc {
	const char *name;
	s16 reg_bank;
	s16 reg;
	};

	struct tegra_pingroup_desc {
	const char *name;
	int funcs[4];
	int func_safe;
	int vddio;
	enum tegra_pin_io io_default;
	s16 tri_bank; /* Register bank the tri_reg exists within */
	s16 mux_bank; /* Register bank the mux_reg exists within */
	s16 pupd_bank; /* Register bank the pupd_reg exists within */
	s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */
	s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */
	s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */
	s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
	s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
	s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
	s8 lock_bit; /* offset of the LOCK bit into mux register bit */
	s8 od_bit; /* offset of the OD bit into mux register bit */
	s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
	};

	typedef void (pinmux_init) (const struct tegra_pingroup_desc *pg,
	int pg_max, const struct tegra_drive_pingroup_desc *pgdrive,
	int *pgdrive_max);

	void tegra20_pinmux_init(const struct tegra_pingroup_desc *pg, int pg_max,
	const struct tegra_drive_pingroup_desc *pgdrive, int pgdrive_max);

	void tegra30_pinmux_init(const struct tegra_pingroup_desc *pg, int pg_max,
	const struct tegra_drive_pingroup_desc *pgdrive, int pgdrive_max);

	int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
	int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);

	void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
	int len);

	void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
	int len);
	void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
	int len);
	void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
	int len);
	void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
	int len, enum tegra_tristate tristate);
	void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
	int len, enum tegra_pullupdown pupd);
	#endif

arch/arm/mach-tegra/pinmux-tegra20-tables.c

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