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Commit b63a1dde authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "defconfig: Enable debug clock controller for sdmshrike"

parents 9e6a5bb4 fd109d35

arch/arm64/boot/dts/qcom/sdmshrike.dtsi

+21 −1
Original line number Diff line number Diff line
@@ -1549,7 +1549,7 @@ 
	};



	clock_dispcc: qcom,dispcc@af00000 {

		compatible = "qcom,dispcc-sm8150";

		compatible = "qcom,dispcc-sm8150", "syscon";

		reg = <0xaf00000 0x20000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&VDD_MMCX_LEVEL>;
@@ -1603,6 +1603,26 @@ 
		reg = <0x182a0018 0x4>;

	};



	mccc_debug: syscon@90b0000 {

		compatible = "syscon";

		reg = <0x90b0000 0x1000>;

	};



	clock_debugcc: qcom,cc-debug {

		compatible = "qcom,debugcc-sdmshrike";

		qcom,gcc = <&clock_gcc>;

		qcom,videocc = <&clock_videocc>;

		qcom,camcc = <&clock_camcc>;

		qcom,dispcc = <&clock_dispcc>;

		qcom,gpucc = <&clock_gpucc>;

		qcom,cpucc = <&cpucc_debug>;

		qcom,npucc = <&clock_npucc>;

		qcom,mccc = <&mccc_debug>;

		clocks = <&clock_rpmh RPMH_CXO_CLK>;

		clock-names = "cxo";

		#clock-cells = <1>;

	};



	tsens0: tsens@c222000 {

		compatible = "qcom,tsens24xx";

		reg = <0xc222000 0x4>,

arch/arm64/configs/vendor/sdmshrike-perf_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -502,6 +502,7 @@ CONFIG_MSM_CLK_RPMH=y 
CONFIG_MSM_GPUCC_SM8150=y

CONFIG_MSM_GCC_SDMSHRIKE=y

CONFIG_MSM_CAMCC_SDMSHRIKE=y

CONFIG_MSM_DEBUGCC_SDMSHRIKE=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_QCOM_APCS_IPC=y

arch/arm64/configs/vendor/sdmshrike_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -525,6 +525,7 @@ CONFIG_MSM_CLK_RPMH=y 
CONFIG_MSM_GPUCC_SM8150=y

CONFIG_MSM_GCC_SDMSHRIKE=y

CONFIG_MSM_CAMCC_SDMSHRIKE=y

CONFIG_MSM_DEBUGCC_SDMSHRIKE=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_QCOM_APCS_IPC=y