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Commit b612eda9 authored by Eric Anholt's avatar Eric Anholt Committed by Dave Airlie
Browse files

i915: GM45 has GM965-style MCH setup. 



Fixes tiling swizzling mode failures that manifest in glReadPixels().

Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 6dbe2772

drivers/gpu/drm/i915/i915_gem_tiling.c

+3 −2
Original line number Diff line number Diff line
@@ -96,7 +96,8 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) 
		 */

		swizzle_x = I915_BIT_6_SWIZZLE_NONE;

		swizzle_y = I915_BIT_6_SWIZZLE_NONE;

	} else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) {

	} else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev) ||

		   IS_GM45(dev)) {

		uint32_t dcc;



		/* On 915-945 and GM965, channel interleave by the CPU is
@@ -118,7 +119,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) 
			    dcc & DCC_CHANNEL_XOR_DISABLE) {

				swizzle_x = I915_BIT_6_SWIZZLE_9_10;

				swizzle_y = I915_BIT_6_SWIZZLE_9;

			} else if (IS_I965GM(dev)) {

			} else if (IS_I965GM(dev) || IS_GM45(dev)) {

				/* GM965 only does bit 11-based channel

				 * randomization

				 */