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Commit b5e501be authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/dp: limit the max supported dp resolution"

parents f2303bc5 fe9d28a2
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+12 −0
Original line number Diff line number Diff line
@@ -785,6 +785,8 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp)

	dp->dp_display.max_pclk_khz = min(dp->parser->max_pclk_khz,
					dp->debug->max_pclk_khz);
	dp->dp_display.max_hdisplay = dp->parser->max_hdisplay;
	dp->dp_display.max_vdisplay = dp->parser->max_vdisplay;

	dp_display_host_init(dp);

@@ -1973,6 +1975,16 @@ static enum drm_mode_status dp_display_validate_mode(
		goto end;
	}

	if (dp_display->max_hdisplay > 0 && dp_display->max_vdisplay > 0 &&
			((mode->hdisplay > dp_display->max_hdisplay) ||
			(mode->vdisplay > dp_display->max_vdisplay))) {
		DP_MST_DEBUG("hdisplay:%d, max-hdisplay:%d",
			mode->hdisplay, dp_display->max_hdisplay);
		DP_MST_DEBUG(" vdisplay:%d, max-vdisplay:%d\n",
			mode->vdisplay, dp_display->max_vdisplay);
		goto end;
	}

	/*
	 * If the connector exists in the mst connector list and if debug is
	 * enabled for that connector, use the mst connector settings from the
+2 −0
Original line number Diff line number Diff line
@@ -76,6 +76,8 @@ struct dp_display {
	bool is_sst_connected;
	bool is_mst_supported;
	u32 max_pclk_khz;
	u32 max_hdisplay;
	u32 max_vdisplay;
	void *dp_mst_prv_info;

	int (*enable)(struct dp_display *dp_display, void *panel);
+6 −0
Original line number Diff line number Diff line
@@ -176,6 +176,12 @@ static int dp_parser_misc(struct dp_parser *parser)
	if (rc)
		parser->max_lclk_khz = DP_MAX_LINK_CLK_KHZ;

	rc = of_property_read_u32(of_node,
		"qcom,max-hdisplay", &parser->max_hdisplay);

	rc = of_property_read_u32(of_node,
		"qcom,max-vdisplay", &parser->max_vdisplay);

	return 0;
}

+4 −0
Original line number Diff line number Diff line
@@ -195,6 +195,8 @@ static inline char *dp_phy_aux_config_type_to_string(u32 cfg_type)
 * @l_pnswap: P/N swap status on each lane
 * @max_pclk_khz: maximum pixel clock supported for the platform
 * @max_lclk_khz: maximum link clock supported for the platform
 * @max_hdisplay: maximum supported horizontal display by the platform for dp
 * @max_vdisplay: maximum supported vertical display by the platform for dp
 * @hw_cfg: DP HW specific settings
 * @has_mst: MST feature enable status
 * @has_mst_sideband: MST sideband feature enable status
@@ -224,6 +226,8 @@ struct dp_parser {
	struct dp_aux_cfg aux_cfg[AUX_CFG_LEN];
	u32 max_pclk_khz;
	u32 max_lclk_khz;
	u32 max_hdisplay;
	u32 max_vdisplay;
	struct dp_hw_cfg hw_cfg;
	bool has_mst;
	bool has_mst_sideband;