Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b5229dbb authored by Olivier Galibert's avatar Olivier Galibert Committed by Andi Kleen
Browse files

[PATCH] i386: Some additional chipset register values validation. 



On i945, a mmconfig range hitting the f0000000-ffffffff zone conflicts
with the APIC registers and others.  Consider it invalid.

On E7520, values 0000 and f000 for the window register are defined
invalid in the documentation.

I haven't seen a bios use these values, but who trusts biosen these
days?

Signed-off-by: default avatarOlivier Galibert <galibert@pobox.com>
Signed-off-by: default avatarAndi Kleen <ak@suse.de>

 arch/i386/pci/mmconfig-shared.c |   25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)
parent 6c2af358

arch/i386/pci/mmconfig-shared.c

+17 −8
Original line number Original line Diff line number Diff line
@@ -60,14 +60,19 @@ static const char __init *pci_mmcfg_e7520(void) 
	u32 win;

	u32 win;

	pci_conf1_read(0, 0, PCI_DEVFN(0,0), 0xce, 2, &win);

	pci_conf1_read(0, 0, PCI_DEVFN(0,0), 0xce, 2, &win);





	win = win & 0xf000;

	if(win == 0x0000 || win == 0xf000)

		pci_mmcfg_config_num = 0;

	else {

		pci_mmcfg_config_num = 1;

		pci_mmcfg_config_num = 1;

		pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);

		pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);

		if (!pci_mmcfg_config)

		if (!pci_mmcfg_config)

			return NULL;

			return NULL;

	pci_mmcfg_config[0].address = (win & 0xf000) << 16;

		pci_mmcfg_config[0].address = win << 16;

		pci_mmcfg_config[0].pci_segment = 0;

		pci_mmcfg_config[0].pci_segment = 0;

		pci_mmcfg_config[0].start_bus_number = 0;

		pci_mmcfg_config[0].start_bus_number = 0;

		pci_mmcfg_config[0].end_bus_number = 255;

		pci_mmcfg_config[0].end_bus_number = 255;

	}





	return "Intel Corporation E7520 Memory Controller Hub";

	return "Intel Corporation E7520 Memory Controller Hub";

}

}
@@ -108,6 +113,10 @@ static const char __init *pci_mmcfg_intel_945(void) 
	if ((pciexbar & mask) & 0x0fffffffU)

	if ((pciexbar & mask) & 0x0fffffffU)

		pci_mmcfg_config_num = 0;

		pci_mmcfg_config_num = 0;





	/* Don't hit the APIC registers and their friends */

	if ((pciexbar & mask) >= 0xf0000000U)

		pci_mmcfg_config_num = 0;



	if (pci_mmcfg_config_num) {

	if (pci_mmcfg_config_num) {

		pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);

		pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);

		if (!pci_mmcfg_config)

		if (!pci_mmcfg_config)