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Commit b4f47a48 authored by Jacob Keller's avatar Jacob Keller Committed by Jeff Kirsher
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ixgbe: use BIT() macro 



Several areas of ixgbe were written before widespread usage of the
BIT(n) macro. With the impending release of GCC 6 and its associated new
warnings, some usages such as (1 << 31) have been noted within the ixgbe
driver source. Fix these wholesale and prevent future issues by simply
using BIT macro instead of hand coded bit shifts.

Also fix a few shifts that are shifting values into place by using the
'u' prefix to indicate unsigned. It doesn't strictly matter in these
cases because we're not shifting by too large a value, but these are all
unsigned values and should be indicated as such.

Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 4319a797

drivers/net/ethernet/intel/ixgbe/ixgbe.h

+34 −34
Original line number Diff line number Diff line
@@ -170,7 +170,7 @@ struct vf_macvlans { 
};



#define IXGBE_MAX_TXD_PWR	14

#define IXGBE_MAX_DATA_PER_TXD	(1 << IXGBE_MAX_TXD_PWR)

#define IXGBE_MAX_DATA_PER_TXD	(1u << IXGBE_MAX_TXD_PWR)



/* Tx Descriptors needed, worst case */

#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
@@ -620,44 +620,44 @@ struct ixgbe_adapter { 
	 * thus the additional *_CAPABLE flags.

	 */

	u32 flags;

#define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 1)

#define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 3)

#define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 4)

#define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 5)

#define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 6)

#define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 8)

#define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 9)

#define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 10)

#define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 11)

#define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 12)

#define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 13)

#define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 14)

#define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 15)

#define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 16)

#define IXGBE_FLAG_NEED_LINK_CONFIG             (u32)(1 << 17)

#define IXGBE_FLAG_FDIR_HASH_CAPABLE            (u32)(1 << 18)

#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE         (u32)(1 << 19)

#define IXGBE_FLAG_FCOE_CAPABLE                 (u32)(1 << 20)

#define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 21)

#define IXGBE_FLAG_SRIOV_CAPABLE                (u32)(1 << 22)

#define IXGBE_FLAG_SRIOV_ENABLED                (u32)(1 << 23)

#define IXGBE_FLAG_MSI_ENABLED			BIT(1)

#define IXGBE_FLAG_MSIX_ENABLED			BIT(3)

#define IXGBE_FLAG_RX_1BUF_CAPABLE		BIT(4)

#define IXGBE_FLAG_RX_PS_CAPABLE		BIT(5)

#define IXGBE_FLAG_RX_PS_ENABLED		BIT(6)

#define IXGBE_FLAG_DCA_ENABLED			BIT(8)

#define IXGBE_FLAG_DCA_CAPABLE			BIT(9)

#define IXGBE_FLAG_IMIR_ENABLED			BIT(10)

#define IXGBE_FLAG_MQ_CAPABLE			BIT(11)

#define IXGBE_FLAG_DCB_ENABLED			BIT(12)

#define IXGBE_FLAG_VMDQ_CAPABLE			BIT(13)

#define IXGBE_FLAG_VMDQ_ENABLED			BIT(14)

#define IXGBE_FLAG_FAN_FAIL_CAPABLE		BIT(15)

#define IXGBE_FLAG_NEED_LINK_UPDATE		BIT(16)

#define IXGBE_FLAG_NEED_LINK_CONFIG		BIT(17)

#define IXGBE_FLAG_FDIR_HASH_CAPABLE		BIT(18)

#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE		BIT(19)

#define IXGBE_FLAG_FCOE_CAPABLE			BIT(20)

#define IXGBE_FLAG_FCOE_ENABLED			BIT(21)

#define IXGBE_FLAG_SRIOV_CAPABLE		BIT(22)

#define IXGBE_FLAG_SRIOV_ENABLED		BIT(23)

#define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE	BIT(24)

#define IXGBE_FLAG_RX_HWTSTAMP_ENABLED		BIT(25)

#define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER	BIT(26)



	u32 flags2;

#define IXGBE_FLAG2_RSC_CAPABLE                 (u32)(1 << 0)

#define IXGBE_FLAG2_RSC_ENABLED                 (u32)(1 << 1)

#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE         (u32)(1 << 2)

#define IXGBE_FLAG2_TEMP_SENSOR_EVENT           (u32)(1 << 3)

#define IXGBE_FLAG2_SEARCH_FOR_SFP              (u32)(1 << 4)

#define IXGBE_FLAG2_SFP_NEEDS_RESET             (u32)(1 << 5)

#define IXGBE_FLAG2_RESET_REQUESTED             (u32)(1 << 6)

#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT        (u32)(1 << 7)

#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP		(u32)(1 << 8)

#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP		(u32)(1 << 9)

#define IXGBE_FLAG2_PTP_PPS_ENABLED		(u32)(1 << 10)

#define IXGBE_FLAG2_PHY_INTERRUPT		(u32)(1 << 11)

#define IXGBE_FLAG2_RSC_CAPABLE			BIT(0)

#define IXGBE_FLAG2_RSC_ENABLED			BIT(1)

#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE		BIT(2)

#define IXGBE_FLAG2_TEMP_SENSOR_EVENT		BIT(3)

#define IXGBE_FLAG2_SEARCH_FOR_SFP		BIT(4)

#define IXGBE_FLAG2_SFP_NEEDS_RESET		BIT(5)

#define IXGBE_FLAG2_RESET_REQUESTED		BIT(6)

#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT	BIT(7)

#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP		BIT(8)

#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP		BIT(9)

#define IXGBE_FLAG2_PTP_PPS_ENABLED		BIT(10)

#define IXGBE_FLAG2_PHY_INTERRUPT		BIT(11)

#define IXGBE_FLAG2_VXLAN_REREG_NEEDED		BIT(12)

#define IXGBE_FLAG2_VLAN_PROMISC		BIT(13)

drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c

+3 −3
Original line number Diff line number Diff line
@@ -792,7 +792,7 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 
	}



	gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);

	gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));

	gheccr &= ~(BIT(21) | BIT(18) | BIT(9) | BIT(6));

	IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);



	/*
@@ -914,10 +914,10 @@ static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, 
	bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));

	if (vlan_on)

		/* Turn on this VLAN id */

		bits |= (1 << bitindex);

		bits |= BIT(bitindex);

	else

		/* Turn off this VLAN id */

		bits &= ~(1 << bitindex);

		bits &= ~BIT(bitindex);

	IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);



	return 0;

drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c

+8 −8
Original line number Diff line number Diff line
@@ -1296,17 +1296,17 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl) 
#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \

do { \

	u32 n = (_n); \

	if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \

	if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n)) \

		common_hash ^= lo_hash_dword >> n; \

	else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \

	else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \

		bucket_hash ^= lo_hash_dword >> n; \

	else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \

	else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n)) \

		sig_hash ^= lo_hash_dword << (16 - n); \

	if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \

	if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n + 16)) \

		common_hash ^= hi_hash_dword >> n; \

	else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \

	else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \

		bucket_hash ^= hi_hash_dword >> n; \

	else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \

	else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n + 16)) \

		sig_hash ^= hi_hash_dword << (16 - n); \

} while (0)
@@ -1440,9 +1440,9 @@ s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 
#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \

do { \

	u32 n = (_n); \

	if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \

	if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \

		bucket_hash ^= lo_hash_dword >> n; \

	if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \

	if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \

		bucket_hash ^= hi_hash_dword >> n; \

} while (0)

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

+15 −15
Original line number Diff line number Diff line
@@ -825,7 +825,7 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 
			 */

			eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>

					    IXGBE_EEC_SIZE_SHIFT);

			eeprom->word_size = 1 << (eeprom_size +

			eeprom->word_size = BIT(eeprom_size +

						 IXGBE_EEPROM_WORD_SIZE_SHIFT);

		}
@@ -1502,7 +1502,7 @@ static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 
	 * Mask is used to shift "count" bits of "data" out to the EEPROM

	 * one bit at a time.  Determine the starting bit based on count

	 */

	mask = 0x01 << (count - 1);

	mask = BIT(count - 1);



	for (i = 0; i < count; i++) {

		/*
@@ -1991,7 +1991,7 @@ static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 
	 */

	vector_reg = (vector >> 5) & 0x7F;

	vector_bit = vector & 0x1F;

	hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);

	hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit);

}



/**
@@ -2921,10 +2921,10 @@ s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 
			mpsar_hi = 0;

		}

	} else if (vmdq < 32) {

		mpsar_lo &= ~(1 << vmdq);

		mpsar_lo &= ~BIT(vmdq);

		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);

	} else {

		mpsar_hi &= ~(1 << (vmdq - 32));

		mpsar_hi &= ~BIT(vmdq - 32);

		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);

	}
@@ -2953,11 +2953,11 @@ s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 


	if (vmdq < 32) {

		mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));

		mpsar |= 1 << vmdq;

		mpsar |= BIT(vmdq);

		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);

	} else {

		mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));

		mpsar |= 1 << (vmdq - 32);

		mpsar |= BIT(vmdq - 32);

		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);

	}

	return 0;
@@ -2978,11 +2978,11 @@ s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 
	u32 rar = hw->mac.san_mac_rar_index;



	if (vmdq < 32) {

		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);

		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq));

		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);

	} else {

		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);

		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));

		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32));

	}



	return 0;
@@ -3082,7 +3082,7 @@ s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 
	 *    bits[4-0]:  which bit in the register

	 */

	regidx = vlan / 32;

	vfta_delta = 1 << (vlan % 32);

	vfta_delta = BIT(vlan % 32);

	vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));



	/* vfta_delta represents the difference between the current value
@@ -3113,12 +3113,12 @@ s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 
	bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));



	/* set the pool bit */

	bits |= 1 << (vind % 32);

	bits |= BIT(vind % 32);

	if (vlan_on)

		goto vlvf_update;



	/* clear the pool bit */

	bits ^= 1 << (vind % 32);

	bits ^= BIT(vind % 32);



	if (!bits &&

	    !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
@@ -3349,9 +3349,9 @@ void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 


	pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));

	if (enable)

		pfvfspoof |= (1 << vf_target_shift);

		pfvfspoof |= BIT(vf_target_shift);

	else

		pfvfspoof &= ~(1 << vf_target_shift);

		pfvfspoof &= ~BIT(vf_target_shift);

	IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);

}

drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c

+2 −2
Original line number Diff line number Diff line
@@ -186,7 +186,7 @@ void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en) 


	for (*pfc_en = 0, tc = 0; tc < MAX_TRAFFIC_CLASS; tc++) {

		if (tc_config[tc].dcb_pfc != pfc_disabled)

			*pfc_en |= 1 << tc;

			*pfc_en |= BIT(tc);

	}

}
@@ -232,7 +232,7 @@ void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *cfg, int direction, 
u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up)

{

	struct tc_configuration *tc_config = &cfg->tc_config[0];

	u8 prio_mask = 1 << up;

	u8 prio_mask = BIT(up);

	u8 tc = cfg->num_tcs.pg_tcs;



	/* If tc is 0 then DCB is likely not enabled or supported */