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Commit b4dd124a authored by Oleg Perelet's avatar Oleg Perelet
Browse files

ARM: dts: msm: extend GPU DCVS table to 5 entries 



Add 2 extra power levels to a640 v2 to keep v1 compatibility
for number of power levels.

Change-Id: I9df2cb4b726f73bcde72ecc9f06610fa6b719c4b
Signed-off-by: default avatarOleg Perelet <operelet@codeaurora.org>
parent e48f6bba

arch/arm64/boot/dts/qcom/sm8150-v2.dtsi

+32 −6
Original line number Diff line number Diff line
@@ -311,6 +311,16 @@ 
&gpu_opp_table {

	compatible = "operating-points-v2";



	opp-700000000 {

		opp-hz = /bits/ 64 <585000000>;

		opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;

	};



	opp-675000000 {

		opp-hz = /bits/ 64 <585000000>;

		opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;

	};



	opp-585000000 {

		opp-hz = /bits/ 64 <585000000>;

		opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
@@ -376,30 +386,46 @@ 


		qcom,gpu-pwrlevel@1 {

			reg = <1>;

			qcom,gpu-freq = <585000000>;

			qcom,bus-freq = <7>;

			qcom,bus-min = <6>;

			qcom,bus-max = <8>;

		};



		qcom,gpu-pwrlevel@2 {

			reg = <2>;

			qcom,gpu-freq = <585000000>;

			qcom,bus-freq = <7>;

			qcom,bus-min = <6>;

			qcom,bus-max = <8>;

		};



		qcom,gpu-pwrlevel@3 {

			reg = <3>;

			qcom,gpu-freq = <427000000>;

			qcom,bus-freq = <6>;

			qcom,bus-min = <5>;

			qcom,bus-max = <7>;

		};



		qcom,gpu-pwrlevel@2 {

			reg = <2>;

		qcom,gpu-pwrlevel@4 {

			reg = <4>;

			qcom,gpu-freq = <345000000>;

			qcom,bus-freq = <3>;

			qcom,bus-min = <3>;

			qcom,bus-max = <5>;

		};



		qcom,gpu-pwrlevel@3 {

			reg = <3>;

		qcom,gpu-pwrlevel@5 {

			reg = <5>;

			qcom,gpu-freq = <257000000>;

			qcom,bus-freq = <2>;

			qcom,bus-min = <1>;

			qcom,bus-max = <3>;

		};



		qcom,gpu-pwrlevel@4 {

			reg = <4>;

		qcom,gpu-pwrlevel@6 {

			reg = <6>;

			qcom,gpu-freq = <0>;

			qcom,bus-freq = <0>;

			qcom,bus-min = <0>;