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Commit b48282c6 authored by Taniya Das's avatar Taniya Das
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clk: msm: Add snapshot of clock framework files 



This is snapshot of the clock framework files as of msm-4.9
'commit cc7a1542d987 ("msm: ipa: Fix assignment warning with clang").

Below is the brief description of the additional changes made:
1. Add COMMON_CLK_MSM config flag for conditional compilation for
   some common files used between COMMON_CLK_MSM and COMMON_CLK_QCOM
   clock framework files.
2. Add reset controller framework files for BCR operation.
3. Add conditional compilation support for FTRACE clock functions
   to maintain compatibility for clock framework based on
   COMMON_CLK_MSM and COMMON_CLK_QCOM.
4. Add files for GDSC operation.
5. Add BCR reset maps.
6. Resolve compilation issue for qti-quin-gvm.

Some PLL HWs require an additional delay for the PLL lock detect
to stabilize after being brought out of reset and SW to poll for
lock detect status. Add delay of 50uSec before polling lock_det
bit by introducing new pll ops.
Also if PLL fails to lock, record additional PLL debug information
in the kernel log before panic().
'commit 90cb5ecd7cfd ("clk: msm: Add delay of 50uSec before polling
 lock_detect status")'.

1:1 is the MN divider preference for DSI PCLK for the regular
24 bpp use-case for display as per hardware recommendation.
Update the divider array to give first priority to 1:1
divider combination.
'commit a270c07a1e21 ("clk: msm: update the fractional divider
 array for DSI PCLK")'.

For some PLLs, there could be need to configure the calibration
L value for auto calibration which PLL would use whenever it will
come out of reset. Add support for the same by writing into
USER_CTL_HI register.
'commit 05bd8759e347 ("clk: msm: Add support to configure
 calibration L value")'.

Change-Id: I4260a9807e5e1b116db8f43fb9cfbbb55a5a8d67
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
Signed-off-by: default avatarSuresh Kumar Allam <allamsuresh@codeaurora.org>
parent e7e90934

Documentation/devicetree/bindings/arm/msm/acpuclock/clock-a7.txt

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* Qualcomm Technologies, Inc. Application CPU clock driver



clock-a7 is the driver for the Root Clock Generator (rcg) hw which controls

the cpu rate. RCGs support selecting one of several clock inputs, as well as

a configurable divider. This hw is different than normal rcgs in that it may

optionally have a register which encodes the maximum rate supported by hw.



Required properties:

- compatible: "qcom,clock-a7-mdm9607"

- reg: pairs of physical address and region size

- reg-names: "rcg-base" is expected

- clock-names: list of names of clock inputs

- qcom,speedX-bin-vZ:

		A table of CPU frequency (Hz) to regulator voltage (uV) mapping.

		Format: <freq uV>

		This represents the max frequency possible for each possible

		power configuration for a CPU that's binned as speed bin X,

		speed bin revision Z. Speed bin values can be between [0-7]

		and the version can be between [0-3].



- cpu-vdd-supply: regulator phandle for cpu power domain.



Optional properties:

- reg-names: "efuse", "efuse1"

- qcom,safe-freq: Frequency in HZ

		When switching rates from A to B, the mux div clock will

		instead switch from A -> safe_freq -> B.

- qcom,enable-opp: This will allow to register the cpu clock with OPP

		framework.



Example:

	qcom,acpuclk@f9011050 {

		compatible = "qcom,clock-a7-8226";

		reg = <0xf9011050 0x8>;

		reg-names = "rcg_base";

		cpu-vdd-supply = <&apc_vreg_corner>;



		clock-names = "clk-4", "clk-5";

		qcom,speed0-bin-v0 =

			<384000000 1150000>,

			<600000000 1200000>;

	};

Documentation/devicetree/bindings/arm/msm/clock-controller.txt

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Qualcomm Technologies, Inc. MSM Clock controller



Qualcomm Technologies, Inc. MSM Clock controller devices contain PLLs, root clock generators

and other clocking hardware blocks that provide stable, low power clocking to

hardware blocks on SOCs. The clock controller device node lists the

power supplies needed to be scaled using the vdd_*-supply property.



Minor differences between hardware revisions are handled in code by re-using

the compatible string to indicate the revision.



Required properties:

- compatible:		Must be one of following,

			"qcom,gcc-mdm9607"

			"qcom,cc-debug-mdm9607"



- reg:			Pairs of physical base addresses and region sizes of

			memory mapped registers.

- reg-names:		Names of the bases for the above registers. Currently,

			there is one expected base: "cc_base". Optional

			reg-names are "apcs_base", "meas", "mmss_base",

			"lpass_base", "apcs_c0_base", "apcs_c1_base",

			"apcs_cci_base", "efuse".



Optional properties:

- vdd_dig-supply:	The digital logic rail supply.

- <pll>_dig-supply:	Some PLLs might have separate digital supply on some

			targets. These properties will be provided on those

			targets for specific PLLs.

- <pll>_analog-supply:	Some PLLs might have separate analog supply on some

			targets. These properties will be provided on those

			targets for specific PLLs.

- vdd_gpu_mx-supply:	MX rail supply for the GPU core.

- #clock_cells:		If this device will also be providing controllable

			clocks, the clock_cells property needs to be specified.

			This will allow the common clock device tree framework

			to recognize _this_ device node as a clock provider.

- qcom,<clk>-corner-<vers>: List of frequency voltage pairs that the clock can

			    operate at. Drivers can use the OPP library API to

			    operate on the list of OPPs registered using these

			    values.

- qcom,<clk>-speedbinX: A table of frequency (Hz) to voltage (corner) mapping

			that represents the max frequency possible for each

			supported voltage level for the clock.

			'X' is the speed bin into which the device falls into -

			a bin will have unique frequency-voltage relationships.

			The value 'X' is read from efuse registers, and the right

			table is picked from multiple possible tables.

- qcom,<clock-name>-opp-handle: phandle references to the devices for which OPP

			table is filled with the clock frequency and voltage

			values.

- qcom,<clock-name>-opp-store-vcorner: phandle references to the devices for

			which OPP table is filled with the clock frequency

			 and voltage corner/level.



Example:

	clock_rpm: qcom,rpmcc@fc4000000 {

		compatible = "qcom,rpmcc-8974";

		reg = <0xfc400000 0x4000>;

		reg-names = "cc_base";

		#clock-cells = <1>;

	};



	clock_gcc: qcom,gcc@fc400000 {

		compatible = "qcom,gcc-8974";

		reg = <0xfc400000 0x4000>;

		reg-names = "cc_base";

		vdd_dig-supply = <&pm8841_s2_corner>;

		#clock-cells = <1>;

	};

Documentation/devicetree/bindings/clock/qcom,msm-clock-controller.txt

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Qualcomm Technologies MSM Clock Controller



Required properties :

- compatible : shall contain "qcom,msm-clock-controller"

- reg : shall contain base register location and length

- reg-names: names of registers listed in the same order as in

	the reg property.

- #clock-cells : shall contain 1

- #reset-cells : shall contain 1



Optional properties :

- vdd_<rail>-supply: The logic rail supply.



Example:

	clock_gcc: qcom,gcc@1800000 {

		compatible = "qcom,msm-clock-controller";

		reg = <0x1800000 0x80000>;

		reg-names = "cc-base";

		#clock-cells = <1>;

		clock-names = "a7_debug_clk";

		clocks = <&clock_a7pll clk_a7_debug_mux>;

	};

arch/arm64/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ config ARM64 
	select ARM_PSCI_FW

	select BUILDTIME_EXTABLE_SORT

	select CLONE_BACKWARDS

	select COMMON_CLK

	select COMMON_CLK if !ARCH_QCOM

	select CPU_PM if (SUSPEND || CPU_IDLE)

	select DCACHE_WORD_ACCESS

	select EDAC_SUPPORT

arch/arm64/Kconfig.platforms

+13 −1
Original line number Diff line number Diff line
@@ -138,12 +138,17 @@ config ARCH_QCOM 
	select MFD_CORE

	select SND_SOC_COMPRESS

	select SND_HWDEP

	select CLKDEV_LOOKUP

	select HAVE_CLK

	select HAVE_CLK_PREPARE

	select PM_OPP

	help

	  This enables support for the ARMv8 based Qualcomm chipsets.



config ARCH_SM8150

	bool "Enable Support for Qualcomm Technologies, Inc. SM8150"

	depends on ARCH_QCOM

	select COMMON_CLK

	select COMMON_CLK_QCOM

	help

	  This enables support for the SM8150 chipset. If you do not
@@ -152,6 +157,7 @@ config ARCH_SM8150 
config ARCH_SDMSHRIKE

	bool "Enable Support for Qualcomm Technologies, Inc. SDMSHRIKE"

	depends on ARCH_QCOM

	select COMMON_CLK

	select COMMON_CLK_QCOM

	help

	  This configuration option enables support to build kernel for
@@ -162,6 +168,7 @@ config ARCH_SDMSHRIKE 
config ARCH_SM6150

	bool "Enable Support for Qualcomm Technologies, Inc. SM6150"

	depends on ARCH_QCOM

	select COMMON_CLK

	select COMMON_CLK_QCOM

	help

	  This enables support for the SM6150 chipset. If you do not
@@ -170,6 +177,7 @@ config ARCH_SM6150 
config ARCH_ATOLL

	bool "Enable Support for Qualcomm Technologies, Inc. ATOLL"

	depends on ARCH_QCOM

	select COMMON_CLK

	select COMMON_CLK_QCOM

	select QTI_PDC_ATOLL

	help
@@ -179,6 +187,7 @@ config ARCH_ATOLL 
config ARCH_QCS405

	bool "Enable Support for Qualcomm Technologies, Inc. QCS405"

	depends on ARCH_QCOM

	select COMMON_CLK

	select COMMON_CLK_QCOM

	help

	 This configuration option enables support to build kernel for
@@ -189,6 +198,7 @@ config ARCH_QCS405 
config ARCH_QCS403

        bool "Enable Support for Qualcomm Technologies, Inc. QCS403"

        depends on ARCH_QCOM

	select COMMON_CLK

	select COMMON_CLK_QCOM

        help

         This configuration option enables support to build kernel for
@@ -199,6 +209,7 @@ config ARCH_QCS403 
config ARCH_SDMMAGPIE

	bool "Enable Support for Qualcomm Technologies, Inc. SDMMAGPIE"

	depends on ARCH_QCOM

	select COMMON_CLK

	select COMMON_CLK_QCOM

	help

	  This enables support for the SDMMAGPIE chipset. If you do not
@@ -207,6 +218,7 @@ config ARCH_SDMMAGPIE 
config ARCH_TRINKET

	bool "Enable Support for Qualcomm Technologies, Inc. TRINKET"

	depends on ARCH_QCOM

	select COMMON_CLK

	select COMMON_CLK_QCOM

	help

	  This enables support for the TRINKET chipset. If you do not