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Commit b3ebd1d8 authored by Olof Johansson's avatar Olof Johansson Committed by Paul Mackerras
Browse files

[POWERPC] powerpc: PA6T cputable entry, PVR value 



Introduce PWRficient PA6T cputable entries and feature bits.

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent 00243000

arch/powerpc/kernel/cputable.c

+14 −0
Original line number Diff line number Diff line
@@ -58,6 +58,9 @@ extern void __restore_cpu_ppc970(void); 
#define COMMON_USER_POWER6	(COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\

				 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \

				 PPC_FEATURE_TRUE_LE)

#define COMMON_USER_PA6T	(COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\

				 PPC_FEATURE_TRUE_LE | \

				 PPC_FEATURE_HAS_ALTIVEC_COMP)

#define COMMON_USER_BOOKE	(PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \

				 PPC_FEATURE_BOOKE)
@@ -286,6 +289,17 @@ struct cpu_spec cpu_specs[] = { 
		.dcache_bsize		= 128,

		.platform		= "ppc-cell-be",

	},

	{	/* PA Semi PA6T */

		.pvr_mask		= 0x7fff0000,

		.pvr_value		= 0x00900000,

		.cpu_name		= "PA6T",

		.cpu_features		= CPU_FTRS_PA6T,

		.cpu_user_features	= COMMON_USER_PA6T,

		.icache_bsize		= 64,

		.dcache_bsize		= 64,

		.num_pmcs		= 6,

		.platform		= "pa6t",

	},

	{	/* default match */

		.pvr_mask		= 0x00000000,

		.pvr_value		= 0x00000000,

include/asm-powerpc/cputable.h

+7 −2
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#define PPC_FEATURE_SMT			0x00004000

#define PPC_FEATURE_ICACHE_SNOOP	0x00002000

#define PPC_FEATURE_ARCH_2_05		0x00001000

#define PPC_FEATURE_PA6T		0x00000800



#define PPC_FEATURE_TRUE_LE		0x00000002

#define PPC_FEATURE_PPC_LE		0x00000001
@@ -332,6 +333,10 @@ extern void do_cpu_ftr_fixups(unsigned long offset); 
	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE)

#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \

	    CPU_FTR_PURR | CPU_FTR_REAL_LE)

#define CPU_FTRS_COMPATIBLE	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)

#endif
@@ -340,7 +345,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset); 
#define CPU_FTRS_POSSIBLE	\

	    (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |	\

	    CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |	\

	    CPU_FTRS_CELL | CPU_FTR_CI_LARGE_PAGE)

	    CPU_FTRS_CELL | CPU_FTRS_PA6T)

#else

enum {

	CPU_FTRS_POSSIBLE =
@@ -379,7 +384,7 @@ enum { 
#define CPU_FTRS_ALWAYS		\

	    (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &	\

	    CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &	\

	    CPU_FTRS_CELL & CPU_FTRS_POSSIBLE)

	    CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)

#else

enum {

	CPU_FTRS_ALWAYS =

include/asm-powerpc/reg.h

+1 −0
Original line number Diff line number Diff line
@@ -592,6 +592,7 @@ 
#define PV_630p	0x0041

#define PV_970MP	0x0044

#define PV_BE		0x0070

#define PV_PA6T		0x0090



/*

 * Number of entries in the SLB. If this ever changes we should handle