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Commit b3a8b751 authored by Lennert Buytenhek's avatar Lennert Buytenhek Committed by Russell King
Browse files

[ARM] 5034/1: fix arm{925,926,940,946} dma_flush_range() in WT mode 



The CPU's dma_flush_range() operation needs to clean+invalidate the
given memory area if the cache is in writeback mode, or do just the
invalidate part if the cache is in writethrough mode, but the current
proc-arm{925,926,940,946} (incorrectly) do a cache clean in the
latter case.  This patch fixes that.

Signed-off-by: default avatarLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent db2c4392

arch/arm/mm/proc-arm925.S

+1 −1
Original line number Diff line number Diff line
@@ -332,7 +332,7 @@ ENTRY(arm925_dma_flush_range) 
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH

	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry

#else

	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry

	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry

#endif

	add	r0, r0, #CACHE_DLINESIZE

	cmp	r0, r1

arch/arm/mm/proc-arm926.S

+1 −1
Original line number Diff line number Diff line
@@ -295,7 +295,7 @@ ENTRY(arm926_dma_flush_range) 
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH

	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry

#else

	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry

	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry

#endif

	add	r0, r0, #CACHE_DLINESIZE

	cmp	r0, r1

arch/arm/mm/proc-arm940.S

+1 −1
Original line number Diff line number Diff line
@@ -222,7 +222,7 @@ ENTRY(arm940_dma_flush_range) 
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH

	mcr	p15, 0, r3, c7, c14, 2		@ clean/flush D entry

#else

	mcr	p15, 0, r3, c7, c10, 2		@ clean D entry

	mcr	p15, 0, r3, c7, c6, 2		@ invalidate D entry

#endif

	subs	r3, r3, #1 << 26

	bcs	2b				@ entries 63 to 0

arch/arm/mm/proc-arm946.S

+1 −1
Original line number Diff line number Diff line
@@ -265,7 +265,7 @@ ENTRY(arm946_dma_flush_range) 
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH

	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry

#else

	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry

	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry

#endif

	add	r0, r0, #CACHE_DLINESIZE

	cmp	r0, r1