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Commit b31fc7af authored by Russell King's avatar Russell King
Browse files

Merge branches 'at91', 'ep93xx', 'kexec', 'iop', 'lmb', 'nomadik', 'nuc',... 

Merge branches 'at91', 'ep93xx', 'kexec', 'iop', 'lmb', 'nomadik', 'nuc', 'pl', 'spear' and 'versatile' into devel
parents f13b1035 4037242c a0fb007b cea0bb1b 7d633975 a9deb137 39ae702c f4f5e28d 7cfe2494 4bd48940 a3e5bb42

arch/arm/Kconfig

+34 −19
Original line number Original line Diff line number Diff line
@@ -10,6 +10,7 @@ config ARM 
	default y

	default y

	select HAVE_AOUT

	select HAVE_AOUT

	select HAVE_IDE

	select HAVE_IDE

	select HAVE_MEMBLOCK

	select RTC_LIB

	select RTC_LIB

	select SYS_SUPPORTS_APM_EMULATION

	select SYS_SUPPORTS_APM_EMULATION

	select GENERIC_ATOMIC64 if (!CPU_32v6K)

	select GENERIC_ATOMIC64 if (!CPU_32v6K)
@@ -24,6 +25,7 @@ config ARM 
	select HAVE_KERNEL_LZMA

	select HAVE_KERNEL_LZMA

	select HAVE_PERF_EVENTS

	select HAVE_PERF_EVENTS

	select PERF_USE_VMALLOC

	select PERF_USE_VMALLOC

	select HAVE_REGS_AND_STACK_ACCESS_API

	help

	help

	  The ARM series is a line of low-power-consumption RISC chip designs

	  The ARM series is a line of low-power-consumption RISC chip designs

	  licensed by ARM Ltd and targeted at embedded applications and

	  licensed by ARM Ltd and targeted at embedded applications and
@@ -704,7 +706,6 @@ config ARCH_SHARK 
config ARCH_LH7A40X

config ARCH_LH7A40X

	bool "Sharp LH7A40X"

	bool "Sharp LH7A40X"

	select CPU_ARM922T

	select CPU_ARM922T

	select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM

	select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM

	select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM

	select ARCH_USES_GETTIMEOFFSET

	select ARCH_USES_GETTIMEOFFSET

	help

	help
@@ -1016,11 +1017,6 @@ endmenu 




source "arch/arm/common/Kconfig"

source "arch/arm/common/Kconfig"





config FORCE_MAX_ZONEORDER

	int

	depends on SA1111

	default "9"



menu "Bus support"

menu "Bus support"





config ARM_AMBA

config ARM_AMBA
@@ -1157,9 +1153,10 @@ config HOTPLUG_CPU 
config LOCAL_TIMERS

config LOCAL_TIMERS

	bool "Use local timer interrupts"

	bool "Use local timer interrupts"

	depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \

	depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \

		REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)

		REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \

		ARCH_U8500 || ARCH_VEXPRESS_CA9X4)

	default y

	default y

	select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)

	select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_VEXPRESS || ARCH_OMAP4 || ARCH_U8500)

	help

	help

	  Enable support for local timers on SMP platforms, rather then the

	  Enable support for local timers on SMP platforms, rather then the

	  legacy IPI broadcast method.  Local timers allows the system

	  legacy IPI broadcast method.  Local timers allows the system
@@ -1226,10 +1223,6 @@ config OABI_COMPAT 
config ARCH_HAS_HOLES_MEMORYMODEL

config ARCH_HAS_HOLES_MEMORYMODEL

	bool

	bool





# Discontigmem is deprecated

config ARCH_DISCONTIGMEM_ENABLE

	bool



config ARCH_SPARSEMEM_ENABLE

config ARCH_SPARSEMEM_ENABLE

	bool

	bool
@@ -1237,13 +1230,7 @@ config ARCH_SPARSEMEM_DEFAULT 
	def_bool ARCH_SPARSEMEM_ENABLE

	def_bool ARCH_SPARSEMEM_ENABLE





config ARCH_SELECT_MEMORY_MODEL

config ARCH_SELECT_MEMORY_MODEL

	def_bool ARCH_DISCONTIGMEM_ENABLE && ARCH_SPARSEMEM_ENABLE

	def_bool ARCH_SPARSEMEM_ENABLE



config NODES_SHIFT

	int

	default "4" if ARCH_LH7A40X

	default "2"

	depends on NEED_MULTIPLE_NODES





config HIGHMEM

config HIGHMEM

	bool "High Memory Support (EXPERIMENTAL)"

	bool "High Memory Support (EXPERIMENTAL)"
@@ -1275,8 +1262,36 @@ config HW_PERF_EVENTS 
	  Enable hardware performance counter support for perf events. If

	  Enable hardware performance counter support for perf events. If

	  disabled, perf events will use software events only.

	  disabled, perf events will use software events only.





config SPARSE_IRQ

	bool "Support sparse irq numbering"

	depends on EXPERIMENTAL

	help

	  This enables support for sparse irqs. This is useful in general

	  as most CPUs have a fairly sparse array of IRQ vectors, which

	  the irq_desc then maps directly on to. Systems with a high

	  number of off-chip IRQs will want to treat this as

	  experimental until they have been independently verified.



	  If you don't know what to do here, say N.



source "mm/Kconfig"

source "mm/Kconfig"





config FORCE_MAX_ZONEORDER

	int "Maximum zone order" if ARCH_SHMOBILE

	range 11 64 if ARCH_SHMOBILE

	default "9" if SA1111

	default "11"

	help

	  The kernel memory allocator divides physically contiguous memory

	  blocks into "zones", where each zone is a power of two number of

	  pages.  This option selects the largest power of two that the kernel

	  keeps in the memory allocator.  If you need to allocate very large

	  blocks of physically contiguous memory, then you may need to

	  increase this value.



	  This config option is actually maximum order plus one. For example,

	  a value of 11 means that the largest free memory block is 2^10 pages.



config LEDS

config LEDS

	bool "Timer and CPU usage LEDs"

	bool "Timer and CPU usage LEDs"

	depends on ARCH_CDB89712 || ARCH_EBSA110 || \

	depends on ARCH_CDB89712 || ARCH_EBSA110 || \

arch/arm/common/gic.c

+46 −0
Original line number Original line Diff line number Diff line
@@ -108,6 +108,51 @@ static void gic_unmask_irq(unsigned int irq) 
	spin_unlock(&irq_controller_lock);

	spin_unlock(&irq_controller_lock);

}

}





static int gic_set_type(unsigned int irq, unsigned int type)

{

	void __iomem *base = gic_dist_base(irq);

	unsigned int gicirq = gic_irq(irq);

	u32 enablemask = 1 << (gicirq % 32);

	u32 enableoff = (gicirq / 32) * 4;

	u32 confmask = 0x2 << ((gicirq % 16) * 2);

	u32 confoff = (gicirq / 16) * 4;

	bool enabled = false;

	u32 val;



	/* Interrupt configuration for SGIs can't be changed */

	if (gicirq < 16)

		return -EINVAL;



	if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)

		return -EINVAL;



	spin_lock(&irq_controller_lock);



	val = readl(base + GIC_DIST_CONFIG + confoff);

	if (type == IRQ_TYPE_LEVEL_HIGH)

		val &= ~confmask;

	else if (type == IRQ_TYPE_EDGE_RISING)

		val |= confmask;



	/*

	 * As recommended by the spec, disable the interrupt before changing

	 * the configuration

	 */

	if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {

		writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);

		enabled = true;

	}



	writel(val, base + GIC_DIST_CONFIG + confoff);



	if (enabled)

		writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);



	spin_unlock(&irq_controller_lock);



	return 0;

}



#ifdef CONFIG_SMP

#ifdef CONFIG_SMP

static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)

static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)

{

{
@@ -161,6 +206,7 @@ static struct irq_chip gic_chip = { 
	.ack		= gic_ack_irq,

	.ack		= gic_ack_irq,

	.mask		= gic_mask_irq,

	.mask		= gic_mask_irq,

	.unmask		= gic_unmask_irq,

	.unmask		= gic_unmask_irq,

	.set_type	= gic_set_type,

#ifdef CONFIG_SMP

#ifdef CONFIG_SMP

	.set_affinity	= gic_set_cpu,

	.set_affinity	= gic_set_cpu,

#endif

#endif

arch/arm/common/sa1111.c

+1 −4
Original line number Original line Diff line number Diff line
@@ -185,13 +185,10 @@ static struct sa1111_dev_info sa1111_devices[] = { 
	},

	},

};

};





void __init sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes)

void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes)

{

{

	unsigned int sz = SZ_1M >> PAGE_SHIFT;

	unsigned int sz = SZ_1M >> PAGE_SHIFT;





	if (node != 0)

		sz = 0;



	size[1] = size[0] - sz;

	size[1] = size[0] - sz;

	size[0] = sz;

	size[0] = sz;

}

}

arch/arm/include/asm/hwcap.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -19,6 +19,7 @@ 
#define HWCAP_NEON	4096

#define HWCAP_NEON	4096

#define HWCAP_VFPv3	8192

#define HWCAP_VFPv3	8192

#define HWCAP_VFPv3D16	16384

#define HWCAP_VFPv3D16	16384

#define HWCAP_TLS	32768





#if defined(__KERNEL__) && !defined(__ASSEMBLY__)

#if defined(__KERNEL__) && !defined(__ASSEMBLY__)

/*

/*

arch/arm/include/asm/irq.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -7,6 +7,8 @@ 
#define irq_canonicalize(i)	(i)

#define irq_canonicalize(i)	(i)

#endif

#endif





#define NR_IRQS_LEGACY	16



/*

/*

 * Use this value to indicate lack of interrupt

 * Use this value to indicate lack of interrupt

 * capability

 * capability