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Commit b2c8946b authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add swr port mapping for sm6150"

parents dd992fb4 1bc42e8f

Documentation/devicetree/bindings/sound/wcd_codec.txt

+19 −0
Original line number Diff line number Diff line
@@ -550,6 +550,14 @@ Tanggu Codec 


Required properties:

 - compatible: "qcom,wcd937x-codec";

 - qcom,rx_swr_ch_map: mapping of swr rx slave port configuration to port_type and also

		corresponding master port type it need to attach.

		format: <port_id, slave_port_type, ch_mask, ch_rate, master_port_type>

		same port_id configurations have to be grouped, and in ascending order.

 - qcom,tx_swr_ch_map: mapping of swr tx slave port configuration to port_type and also

		corresponding master port type it need to attach.

		format: <port_id,slave_port_type, ch_mask, ch_rate, master_port_type>

		same port_id configurations have to be grouped, and in ascending order.

 - qcom,wcd-rst-gpio-node: Phandle reference to the DT node having codec reset gpio

                        configuration. If this property is not defined, it is

                        expected to atleast define "qcom,cdc-reset-gpio" property.
@@ -585,6 +593,17 @@ Optional properties: 
Example:

wcd937x_codec: wcd937x-codec {

	compatible = "qcom,wcd937x-codec";

	qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,

		<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x3 0 CLSH>,

		<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,

		<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,

		<4 DSD_R 0x2 0 DSD_R>;

	qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,

		<1 ADC2 0x1 0 ADC3>, <1 ADC3 0x2 0 ADC4>,

		<2 DMIC0 0x1 0 DMIC0>, <2 DMIC1 0x2 0 DMIC1>,

		<2 MBHC 0x4 0 DMIC2>, <3 DMIC2 0x1 0 DMIC4>,

		<3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>,

		<3 DMIC5 0x8 0 DMIC7>;



	qcom,wcd-rst-gpio-node = <&wcd937x_rst_gpio>;

	qcom,rx-slave = <&wcd937x_rx_slave>;

Documentation/devicetree/bindings/soundwire/swr-mstr-ctrl.txt

+4 −0
Original line number Diff line number Diff line
@@ -22,6 +22,9 @@ Required properties: 
	which the swr-devid is <0x0 0x032000> where 0x03 represents

	device Unique_ID, 0x20 represents Part_Id1 and 0x00

	represents part_Id2.

Optional properties:

- mipi-sdw-clock-stop-mode0-supported : should be set to 1 if all

	the slaves under the master supports clock stop mode 0



 Example:
@@ -46,4 +49,5 @@ swr0: swr_master { 
			compatible = "qcom,wsa881x";

			reg = <0x00 0x042000>;

		};

		mipi-sdw-clock-stop-mode0-supported = <0>;

	};

arch/arm64/boot/dts/qcom/qcs405-wsa881x.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ 
			<6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,

			<8 SPKR_R_VI 0x3>;

		qcom,swr-num-dev = <2>;



		qcom,swr_master_id = <1>;

		wsa881x_0211: wsa881x@20170211 {

			compatible = "qcom,wsa881x";

			reg = <0x0 0x20170211>;

arch/arm64/boot/dts/qcom/sm6150-audio-overlay.dtsi

+75 −31
Original line number Diff line number Diff line
@@ -20,56 +20,89 @@ 


#include "sm6150-lpi.dtsi"

#include <dt-bindings/clock/qcom,audio-ext-clk.h>

#include <dt-bindings/sound/audio-codec-port-types.h>



&bolero {

	qcom,num-macros = <4>;

	qcom,va-without-decimation;

	wsa_macro: wsa-macro@62F00000 {

		compatible = "qcom,wsa-macro";

		reg = <0x62F00000 0x0>;

		clock-names = "wsa_core_clk", "wsa_npl_clk";

		clocks = <&clock_audio_wsa_1 0>,

			 <&clock_audio_wsa_2 0>;

		qcom,wsa-swr-gpios = <&wsa_swr_gpios>;

	tx_macro: tx-macro@62ec0000 {

		compatible = "qcom,tx-macro";

		reg = <0x62ec0000 0x0>;

		clock-names = "tx_core_clk", "tx_npl_clk";

		clocks = <&clock_audio_tx_1 0>,

			 <&clock_audio_tx_2 0>;

		qcom,tx-swr-gpios = <&tx_swr_gpios>;

		qcom,tx-dmic-sample-rate = <4800000>;

		swr_2: tx_swr_master {

			compatible = "qcom,swr-mstr";

			#address-cells = <2>;

			#size-cells = <0>;

			qcom,swr_master_id = <3>;

			swrm-io-base = <0x62ed0000 0x0>;

			interrupts = <0 137 0>, <0 528 0>;

			interrupt-names = "swr_master_irq", "swr_wake_irq";

			qcom,swr-num-ports = <5>;

			qcom,swr-port-mapping = <1 PCM_OUT1 0xF>,

				<2 ADC1 0x1>, <2 ADC2 0x2>,

				<3 ADC3 0x1>, <3 ADC4 0x2>,

				<4 DMIC0 0x1>, <4 DMIC1 0x2>,

				<4 DMIC2 0x4>, <4 DMIC3 0x8>,

				<5 DMIC4 0x1>, <5 DMIC5 0x2>,

				<5 DMIC6 0x4>, <5 DMIC7 0x8>;

			qcom,swr-num-dev = <1>;

			qcom,swr-clock-stop-mode0 = <1>;

			wcd937x_tx_slave: wcd937x-tx-slave {

				compatible = "qcom,wcd937x-slave";

				reg = <0x0 0x01170223>;

			};

		};



	va_macro: va-macro@62F20000 {

		compatible = "qcom,va-macro";

		reg = <0x62F20000 0x0>;

		clock-names = "va_core_clk";

		clocks = <&clock_audio_va 0>;

	};



	rx_macro: rx-macro@62EE0000 {

	rx_macro: rx-macro@62ee0000 {

		compatible = "qcom,rx-macro";

		reg = <0x62EE0000 0x0>;

		reg = <0x62ee0000 0x0>;

		clock-names = "rx_core_clk", "rx_npl_clk";

		clocks = <&clock_audio_rx_1 0>,

			 <&clock_audio_rx_2 0>;

		qcom,rx-swr-gpios = <&rx_swr_gpios>;

		qcom,rx_mclk_mode_muxsel = <0x62C25020>;

		qcom,rx_mclk_mode_muxsel = <0x62c25020>;

		swr_1: rx_swr_master {

			compatible = "qcom,swr-mstr";

			#address-cells = <2>;

			#size-cells = <0>;

			qcom,swr_master_id = <2>;

			swrm-io-base = <0x62ef0000 0x0>;

			interrupts = <0 138 0>;

			interrupt-names = "swr_master_irq";

			qcom,swr-num-ports = <5>;

			qcom,swr-port-mapping = <1 HPH_L 0x1>,

				<1 HPH_R 0x2>, <2 CLSH 0x3>,

				<3 COMP_L 0x1>, <3 COMP_R 0x2>,

				<4 LO 0x1>, <5 DSD_L 0x1>,

				<5 DSD_R 0x2>;

			qcom,swr-num-dev = <1>;

			qcom,swr-clock-stop-mode0 = <1>;

			wcd937x_rx_slave: wcd937x-rx-slave {

				compatible = "qcom,wcd937x-slave";

				reg = <0x0 0x01170224>;

			};

		};

	};



	tx_macro: tx-macro@62EC0000 {

		compatible = "qcom,tx-macro";

		reg = <0x62EC0000 0x0>;

		clock-names = "tx_core_clk", "tx_npl_clk";

		clocks = <&clock_audio_tx_1 0>,

			 <&clock_audio_tx_2 0>;

		qcom,tx-swr-gpios = <&tx_swr_gpios>;

		qcom,tx-dmic-sample-rate = <4800000>;

		swr_2: tx_swr_master {

			compatible = "qcom,swr-mstr";

			wcd937x_tx_slave: wcd937x-tx-slave {

				compatible = "qcom,wcd937x-slave";

			};

	wsa_macro: wsa-macro@62f00000 {

		compatible = "qcom,wsa-macro";

		reg = <0x62f00000 0x0>;

		clock-names = "wsa_core_clk", "wsa_npl_clk";

		clocks = <&clock_audio_wsa_1 0>,

			 <&clock_audio_wsa_2 0>;

		qcom,wsa-swr-gpios = <&wsa_swr_gpios>;

	};



	va_macro: va-macro@62f20000 {

		compatible = "qcom,va-macro";

		reg = <0x62f20000 0x0>;

		clock-names = "va_core_clk";

		clocks = <&clock_audio_va 0>;

	};

};
@@ -125,6 +158,17 @@ 
&soc {

	wcd937x_codec: wcd937x-codec {

		compatible = "qcom,wcd937x-codec";

		qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,

			<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x3 0 CLSH>,

			<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,

			<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,

			<4 DSD_R 0x2 0 DSD_R>;

		qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,

			<1 ADC2 0x1 0 ADC3>, <1 ADC3 0x2 0 ADC4>,

			<2 DMIC0 0x1 0 DMIC0>, <2 DMIC1 0x2 0 DMIC1>,

			<2 MBHC 0x4 0 DMIC2>, <3 DMIC2 0x1 0 DMIC4>,

			<3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>,

			<3 DMIC5 0x8 0 DMIC7>;



		qcom,wcd-rst-gpio-node = <&wcd937x_rst_gpio>;

		qcom,rx-slave = <&wcd937x_rx_slave>;

arch/arm64/boot/dts/qcom/sm6150-audio.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ 
#include "msm-audio-lpass.dtsi"



&msm_audio_ion {

	iommus = <&apps_smmu 0x1b21 0x0>;

	iommus = <&apps_smmu 0x1721 0x0>;

	qcom,smmu-sid-mask = /bits/ 64 <0xf>;

};