Commit b293fca4 authored Nov 15, 2017 by Linus Torvalds

Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of...

Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux

Pull RISC-V architecture support from Palmer Dabbelt:
"This contains the core RISC-V Linux port, which has been through nine
rounds of review on various mailing lists. The port is not complete:
there's some cleanup patches moving through the review process, a
whole bunch of drivers that need some work, and a lot of feature
additions that will be needed.

The patches contained in this tag have been through nine rounds of
review on the various mailing lists. I have some outstanding cleanup
patches, but since there's been so much review on these patches I
thought it would be best to submit them as-is and then submit explicit
cleanup patches so everyone can review them. This first patch set is
big enough that it's a bit of a pain to constantly rewrite, and it's
caused a few headaches with various contributors.

The port is definately a work in progress. While what's there builds
and boots with 4.14, it's a bit hard to actually see anything happen
because there are no device drivers yet. I maintain a staging branch
that contains all the device drivers and cleanup that actually works,
but those patches won't all be ready for a while. I'd like to get what
we currently have into your tree so everyone can start working from a
single base -- of particular importance is allowing the glibc
upstreaming process to proceed so we can sort out any possibly
lingering user-visible ABI problems we might have.

Copied below is the ChangeLog that contains the history of this patch
set:

(v9) As per suggestions on our v8 patch set, I've split the core
architecture code out from our drivers and would like to submit
this patch set to be included into linux-next, with the goal
being to be merged in during the next merge window. This patch
set is based on 4.14-rc2, but if it's better to have it based on
something else then I can change it around.

This patch set contains just the core arch code for RISC-V, so
while it builds an nominally boots, you can't print or take an
interrupt so it's not that useful. If you're looking to actually
boot a system it would probably be better to use the full patch
set listed below.

We've collected a handful of tags from reviewers, and the
remainder of the patch set only got minimal feedback last time.
Here's what changed:

- We now use the device tree to initialize the timer driver so
it's less tighly coupled with the arch port.

- I cleaned up the defconfigs -- there's actually now just one,
and it's empty. For now I think we're OK with what the kernel
sets as defaults, but I anticipate we'll begin to expand this
as people start to use the port more.

- The VDSO symbols version is sane.

- We WFI while spinning in the boot loop.

- A handful of comments have been added.

While there are still a handful of FIXMEs in this patch set,
we've started to get enough interest from various users and
contributors that maintaining an out of tree patch set is
starting to become a big burden. Hopefully the patches are good
enough to merge now, which will at least get everyone working in
a more reasonable manner as we clean up the remaining issues.

(v8) I know it may not be the ideal time to submit a patch set right
now, as it's the middle of the merge window, but things have
calmed down quite a bit in the last month so I thought it would
be good to get everyone on the same page. There's been a handful
of changes since the last patch set, but most of them are fairly
minor:

- We changed PAGE_OFFSET to allowing mapping more physical
memory on 64-bit systems. This is user configurable, as it
triggers a different code model that generates slightly less
efficient code.

- The device tree binding documentation is back, I'd managed to
lose it at some point.

- We now pass the atomic64 test suite

- The SBI timer driver has been refactored.

(v7) It's been a while since my last patch set, but the changes han
been fairly minimal:

- The PCI cleanup patches have been dropped, we'll do them as a
separate patch set later.

- We've the Kconfig entries from CONFIG_ISA_* to
CONFIG_RISCV_ISA_*, to make grep easier.

- There have been a handful of memory model related tweaks in
I/O land, particularly relating the PCI and the upcoming
platform specification. There are significant comments in the
relevant files. This is still a WIP, but I think we're close
to getting as good as we're going to get until we end up with
some more specifications.

(v6) As it's been only a day since the v5 patch set, the changes are
pretty minimal:

- The patch set is now based on linux-next/master, which I
believe is a better base now that we're getting closer to
upstream.

- EARLY_PRINTK is no longer an option. Since the SBI console is
reasonable, there's no penalty to enabling it (and thus no
benefit to disabling it).

- The mmap syscalls were refactored a bit.

(v5) Things have really started to calm down, so this is fairly
similar to the v4 patch set. The most interesting changes
include:

- We've moved back to a single patch set.

- SMP support has been fixed, I was accidentally running on a
non-SMP configuration. There were various mistakes all over
the tree as a result of this.

- The cmpxchg syscalls have been removed, as they were deemed a
bad idea. As a result, RISC-V Linux systems mandate the A
extension. The corresponding Kconfig entry to enable builds
on non-A systems has been removed.

- A few more atomic fixes: mostly fence changes, but those
resulted in a handful of additional macros that were no
longer necessary.

- riscv_early_sie has been removed.

(v4) There have only been a few changes since the v3 patch set:

- The cmpxchg64 syscall is no longer enabled on 32-bit systems.
It's not possible to provide this on SMP systems, and it's
not necessary as glibc knows not to call it.

- We provide a ELF_HWCAP so users can determine the ISA of the
machine the kernel is running on.

- The multi-line comments are in a better form.

- There were a handful of headers that could be replaced with
the asm-generic versions, and a few unnecessary definitions.

- We no longer use printk, but instead use pr_*.

- A few Kconfig and defconfig entries have been cleaned up.

(v3) A highlight of the changes since the v2 patch set includes:

- We've split out all our drivers into separate patch sets,
which I've already sent out to the relevant maintainers. I
haven't included those patches in this patch set, but some of
them are necessary to build our port.

- The patch set is now split up differently: rather than being
split per directory it is split per topic. Hopefully this
will make it easier to review the port on the mailing list.
The split is a bit rough, so you probably still want to look
at the patch set as a whole.

- atomic.h has been completely rewritten and is hopefully now
correct. I've attempted to sanitize the various other memory
model related code as well, and I think it should all be sane
now aside from a handful of FIXMEs commented in the code.

- We've changed the cmpexchg syscall to always exist and to not
be multiplexed. There is also a VDSO entry for compare and
exchange, which allows kernels with the A extension to
execute user code without the A extension reasonably fast.

- Our user-visible register state now contains enough space for
the Q extension for 128-bit floating point, as well as a few
words to allow extensibility to future ISA extensions like
the eventual V extension for vectors.

- A handful of driver cleanups, but these have been split into
separate patch sets now so I won't duplicate them here.

(v2) A highlight of the changes since the v1 patch set includes:

- We've split out our drivers into the right places, which
means now there's a lot more patches. I'll be submitting
these patches to various subsystem maintainers and including
them in any future RISC-V patch sets until they've been
merged.

- The SBI console driver has been completely rewritten to use
the HVC helpers and is now significantly smaller.

- We've begun to use weaker barriers as opposed to just the big
"fence". There's still some work to do here, specifically:
- We need fences in the relaxed MMIO functions.
- The non-relaxed MMIO functions are missing R/W bits on their fences.
- Many AMOs need the aq and rl bits set.

- We now have thread_info in task_struct. As a result, sscratch
now contains TP instead of SP. This was necessary because
thread_info is no longer on the stack.

- A few shared routines have been added that we use instead of
creating another arch copy"

Reviewed-by: Arnd Bergmann <arnd@arndb.de>

* tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux:
RISC-V: Build Infrastructure
RISC-V: User-facing API
RISC-V: Paging and MMU
RISC-V: Device, timer, IRQs, and the SBI
RISC-V: Task implementation
RISC-V: ELF and module implementation
RISC-V: Generic library routines and assembly
RISC-V: Atomic and Locking Code
RISC-V: Init and Halt Code
dt-bindings: RISC-V CPU Bindings
lib: Add shared copies of some GCC library routines
MAINTAINERS: Add RISC-V

parents 0ef76878 fbe934d6

Documentation/devicetree/bindings/riscv/cpus.txt

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			===================
			RISC-V CPU Bindings
			===================

			The device tree allows to describe the layout of CPUs in a system through
			the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
			defining properties for every cpu.

			Bindings for CPU nodes follow the Devicetree Specification, available from:

			https://www.devicetree.org/specifications/

			with updates for 32-bit and 64-bit RISC-V systems provided in this document.

			===========
			Terminology
			===========

			This document uses some terminology common to the RISC-V community that is not
			widely used, the definitions of which are listed here:

			* hart: A hardware execution context, which contains all the state mandated by
			the RISC-V ISA: a PC and some registers. This terminology is designed to
			disambiguate software's view of execution contexts from any particular
			microarchitectural implementation strategy. For example, my Intel laptop is
			described as having one socket with two cores, each of which has two hyper
			threads. Therefore this system has four harts.

			=====================================
			cpus and cpu node bindings definition
			=====================================

			The RISC-V architecture, in accordance with the Devicetree Specification,
			requires the cpus and cpu nodes to be present and contain the properties
			described below.

			- cpus node

			Description: Container of cpu nodes

			The node name must be "cpus".

			A cpus node must define the following properties:

			- #address-cells
			Usage: required
			Value type: <u32>
			Definition: must be set to 1
			- #size-cells
			Usage: required
			Value type: <u32>
			Definition: must be set to 0

			- cpu node

			Description: Describes a hart context

			PROPERTIES

			- device_type
			Usage: required
			Value type: <string>
			Definition: must be "cpu"
			- reg
			Usage: required
			Value type: <u32>
			Definition: The hart ID of this CPU node
			- compatible:
			Usage: required
			Value type: <stringlist>
			Definition: must contain "riscv", may contain one of
			"sifive,rocket0"
			- mmu-type:
			Usage: optional
			Value type: <string>
			Definition: Specifies the CPU's MMU type. Possible values are
			"riscv,sv32"
			"riscv,sv39"
			"riscv,sv48"
			- riscv,isa:
			Usage: required
			Value type: <string>
			Definition: Contains the RISC-V ISA string of this hart. These
			ISA strings are defined by the RISC-V ISA manual.

			Example: SiFive Freedom U540G Development Kit
			---------------------------------------------

			This system contains two harts: a hart marked as disabled that's used for
			low-level system tasks and should be ignored by Linux, and a second hart that
			Linux is allowed to run on.

			cpus {
			#address-cells = <1>;
			#size-cells = <0>;
			timebase-frequency = <1000000>;
			cpu@0 {
			clock-frequency = <1600000000>;
			compatible = "sifive,rocket0", "riscv";
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <128>;
			i-cache-size = <16384>;
			next-level-cache = <&L15 &L0>;
			reg = <0>;
			riscv,isa = "rv64imac";
			status = "disabled";
			L10: interrupt-controller {
			#interrupt-cells = <1>;
			compatible = "riscv,cpu-intc";
			interrupt-controller;
			};
			};
			cpu@1 {
			clock-frequency = <1600000000>;
			compatible = "sifive,rocket0", "riscv";
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <32>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <32>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&L15 &L0>;
			reg = <1>;
			riscv,isa = "rv64imafdc";
			status = "okay";
			tlb-split;
			L13: interrupt-controller {
			#interrupt-cells = <1>;
			compatible = "riscv,cpu-intc";
			interrupt-controller;
			};
			};
			};

			Example: Spike ISA Simulator with 1 Hart
			----------------------------------------

			This device tree matches the Spike ISA golden model as run with `spike -p1`.

			cpus {
			cpu@0 {
			device_type = "cpu";
			reg = <0x00000000>;
			status = "okay";
			compatible = "riscv";
			riscv,isa = "rv64imafdc";
			mmu-type = "riscv,sv48";
			clock-frequency = <0x3b9aca00>;
			interrupt-controller {
			#interrupt-cells = <0x00000001>;
			interrupt-controller;
			compatible = "riscv,cpu-intc";
			}
			}
			}

MAINTAINERS

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	@@ -11534,6 +11534,16 @@ S: Maintained
	F: drivers/mtd/nand/r852.c		F: drivers/mtd/nand/r852.c
	F: drivers/mtd/nand/r852.h		F: drivers/mtd/nand/r852.h

			RISC-V ARCHITECTURE
			M: Palmer Dabbelt <palmer@sifive.com>
			M: Albert Ou <albert@sifive.com>
			L: patches@groups.riscv.org
			T: git https://github.com/riscv/riscv-linux
			S: Supported
			F: arch/riscv/
			K: riscv
			N: riscv

	ROCCAT DRIVERS		ROCCAT DRIVERS
	M: Stefan Achatz <erazor_de@users.sourceforge.net>		M: Stefan Achatz <erazor_de@users.sourceforge.net>
	W: http://sourceforge.net/projects/roccat/		W: http://sourceforge.net/projects/roccat/

Makefile

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	@@ -226,7 +226,8 @@ SUBARCH := $(shell uname -m \| sed -e s/i.86/x86/ -e s/x86_64/x86/ \
	-e s/arm.*/arm/ -e s/sa110/arm/ \		-e s/arm.*/arm/ -e s/sa110/arm/ \
	-e s/s390x/s390/ -e s/parisc64/parisc/ \		-e s/s390x/s390/ -e s/parisc64/parisc/ \
	-e s/ppc./powerpc/ -e s/mips./mips/ \		-e s/ppc./powerpc/ -e s/mips./mips/ \
	-e s/sh[234]./sh/ -e s/aarch64./arm64/ )		-e s/sh[234]./sh/ -e s/aarch64./arm64/ \
			-e s/riscv.*/riscv/)

	# Cross compiling and selecting different set of gcc/bin-utils		# Cross compiling and selecting different set of gcc/bin-utils
	# ---------------------------------------------------------------------------		# ---------------------------------------------------------------------------

arch/riscv/Kconfig

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			#
			# For a description of the syntax of this configuration file,
			# see Documentation/kbuild/kconfig-language.txt.
			#

			config RISCV
			def_bool y
			select OF
			select OF_EARLY_FLATTREE
			select OF_IRQ
			select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
			select ARCH_WANT_FRAME_POINTERS
			select CLONE_BACKWARDS
			select COMMON_CLK
			select GENERIC_CLOCKEVENTS
			select GENERIC_CPU_DEVICES
			select GENERIC_IRQ_SHOW
			select GENERIC_PCI_IOMAP
			select GENERIC_STRNCPY_FROM_USER
			select GENERIC_STRNLEN_USER
			select GENERIC_SMP_IDLE_THREAD
			select GENERIC_ATOMIC64 if !64BIT \|\| !RISCV_ISA_A
			select ARCH_WANT_OPTIONAL_GPIOLIB
			select HAVE_MEMBLOCK
			select HAVE_DMA_API_DEBUG
			select HAVE_DMA_CONTIGUOUS
			select HAVE_GENERIC_DMA_COHERENT
			select IRQ_DOMAIN
			select NO_BOOTMEM
			select RISCV_ISA_A if SMP
			select SPARSE_IRQ
			select SYSCTL_EXCEPTION_TRACE
			select HAVE_ARCH_TRACEHOOK
			select MODULES_USE_ELF_RELA if MODULES
			select THREAD_INFO_IN_TASK
			select RISCV_IRQ_INTC
			select RISCV_TIMER

			config MMU
			def_bool y

			# even on 32-bit, physical (and DMA) addresses are > 32-bits
			config ARCH_PHYS_ADDR_T_64BIT
			def_bool y

			config ARCH_DMA_ADDR_T_64BIT
			def_bool y

			config PAGE_OFFSET
			hex
			default 0xC0000000 if 32BIT && MAXPHYSMEM_2GB
			default 0xffffffff80000000 if 64BIT && MAXPHYSMEM_2GB
			default 0xffffffe000000000 if 64BIT && MAXPHYSMEM_128GB

			config STACKTRACE_SUPPORT
			def_bool y

			config RWSEM_GENERIC_SPINLOCK
			def_bool y

			config GENERIC_BUG
			def_bool y
			depends on BUG
			select GENERIC_BUG_RELATIVE_POINTERS if 64BIT

			config GENERIC_BUG_RELATIVE_POINTERS
			bool

			config GENERIC_CALIBRATE_DELAY
			def_bool y

			config GENERIC_CSUM
			def_bool y

			config GENERIC_HWEIGHT
			def_bool y

			config PGTABLE_LEVELS
			int
			default 3 if 64BIT
			default 2

			config HAVE_KPROBES
			def_bool n

			config DMA_NOOP_OPS
			def_bool y

			menu "Platform type"

			choice
			prompt "Base ISA"
			default ARCH_RV64I
			help
			This selects the base ISA that this kernel will traget and must match
			the target platform.

			config ARCH_RV32I
			bool "RV32I"
			select CPU_SUPPORTS_32BIT_KERNEL
			select 32BIT
			select GENERIC_ASHLDI3
			select GENERIC_ASHRDI3
			select GENERIC_LSHRDI3

			config ARCH_RV64I
			bool "RV64I"
			select CPU_SUPPORTS_64BIT_KERNEL
			select 64BIT

			endchoice

			# We must be able to map all physical memory into the kernel, but the compiler
			# is still a bit more efficient when generating code if it's setup in a manner
			# such that it can only map 2GiB of memory.
			choice
			prompt "Kernel Code Model"
			default CMODEL_MEDLOW if 32BIT
			default CMODEL_MEDANY if 64BIT

			config CMODEL_MEDLOW
			bool "medium low code model"
			config CMODEL_MEDANY
			bool "medium any code model"
			endchoice

			choice
			prompt "Maximum Physical Memory"
			default MAXPHYSMEM_2GB if 32BIT
			default MAXPHYSMEM_2GB if 64BIT && CMODEL_MEDLOW
			default MAXPHYSMEM_128GB if 64BIT && CMODEL_MEDANY

			config MAXPHYSMEM_2GB
			bool "2GiB"
			config MAXPHYSMEM_128GB
			depends on 64BIT && CMODEL_MEDANY
			bool "128GiB"
			endchoice


			config SMP
			bool "Symmetric Multi-Processing"
			help
			This enables support for systems with more than one CPU. If
			you say N here, the kernel will run on single and
			multiprocessor machines, but will use only one CPU of a
			multiprocessor machine. If you say Y here, the kernel will run
			on many, but not all, single processor machines. On a single
			processor machine, the kernel will run faster if you say N
			here.

			If you don't know what to do here, say N.

			config NR_CPUS
			int "Maximum number of CPUs (2-32)"
			range 2 32
			depends on SMP
			default "8"

			config CPU_SUPPORTS_32BIT_KERNEL
			bool
			config CPU_SUPPORTS_64BIT_KERNEL
			bool

			choice
			prompt "CPU Tuning"
			default TUNE_GENERIC

			config TUNE_GENERIC
			bool "generic"

			endchoice

			config RISCV_ISA_C
			bool "Emit compressed instructions when building Linux"
			default y
			help
			Adds "C" to the ISA subsets that the toolchain is allowed to emit
			when building Linux, which results in compressed instructions in the
			Linux binary.

			If you don't know what to do here, say Y.

			config RISCV_ISA_A
			def_bool y

			endmenu

			menu "Kernel type"

			choice
			prompt "Kernel code model"
			default 64BIT

			config 32BIT
			bool "32-bit kernel"
			depends on CPU_SUPPORTS_32BIT_KERNEL
			help
			Select this option to build a 32-bit kernel.

			config 64BIT
			bool "64-bit kernel"
			depends on CPU_SUPPORTS_64BIT_KERNEL
			help
			Select this option to build a 64-bit kernel.

			endchoice

			source "mm/Kconfig"

			source "kernel/Kconfig.preempt"

			source "kernel/Kconfig.hz"

			endmenu

			menu "Bus support"

			config PCI
			bool "PCI support"
			select PCI_MSI
			help
			This feature enables support for PCI bus system. If you say Y
			here, the kernel will include drivers and infrastructure code
			to support PCI bus devices.

			If you don't know what to do here, say Y.

			config PCI_DOMAINS
			def_bool PCI

			config PCI_DOMAINS_GENERIC
			def_bool PCI

			source "drivers/pci/Kconfig"

			endmenu

			source "init/Kconfig"

			source "kernel/Kconfig.freezer"

			menu "Executable file formats"

			source "fs/Kconfig.binfmt"

			endmenu

			menu "Power management options"

			source kernel/power/Kconfig

			endmenu

			source "net/Kconfig"

			source "drivers/Kconfig"

			source "fs/Kconfig"

			menu "Kernel hacking"

			config CMDLINE_BOOL
			bool "Built-in kernel command line"
			help
			For most platforms, it is firmware or second stage bootloader
			that by default specifies the kernel command line options.
			However, it might be necessary or advantageous to either override
			the default kernel command line or add a few extra options to it.
			For such cases, this option allows hardcoding command line options
			directly into the kernel.

			For that, choose 'Y' here and fill in the extra boot parameters
			in CONFIG_CMDLINE.

			The built-in options will be concatenated to the default command
			line if CMDLINE_OVERRIDE is set to 'N'. Otherwise, the default
			command line will be ignored and replaced by the built-in string.

			config CMDLINE
			string "Built-in kernel command string"
			depends on CMDLINE_BOOL
			default ""
			help
			Supply command-line options at build time by entering them here.

			config CMDLINE_OVERRIDE
			bool "Built-in command line overrides bootloader arguments"
			depends on CMDLINE_BOOL
			help
			Set this option to 'Y' to have the kernel ignore the bootloader
			or firmware command line. Instead, the built-in command line
			will be used exclusively.

			If you don't know what to do here, say N.

			config EARLY_PRINTK
			def_bool y

			source "lib/Kconfig.debug"

			config CMDLINE_BOOL
			bool
			endmenu

			source "security/Kconfig"

			source "crypto/Kconfig"

			source "lib/Kconfig"

arch/riscv/Makefile

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			# This file is included by the global makefile so that you can add your own
			# architecture-specific flags and dependencies. Remember to do have actions
			# for "archclean" and "archdep" for cleaning up and making dependencies for
			# this architecture
			#
			# This file is subject to the terms and conditions of the GNU General Public
			# License. See the file "COPYING" in the main directory of this archive
			# for more details.
			#

			LDFLAGS :=
			OBJCOPYFLAGS := -O binary
			LDFLAGS_vmlinux :=
			KBUILD_AFLAGS_MODULE += -fPIC
			KBUILD_CFLAGS_MODULE += -fPIC

			KBUILD_DEFCONFIG = defconfig

			export BITS
			ifeq ($(CONFIG_ARCH_RV64I),y)
			BITS := 64
			UTS_MACHINE := riscv64

			KBUILD_CFLAGS += -mabi=lp64
			KBUILD_AFLAGS += -mabi=lp64
			KBUILD_MARCH = rv64im
			LDFLAGS += -melf64lriscv
			else
			BITS := 32
			UTS_MACHINE := riscv32

			KBUILD_CFLAGS += -mabi=ilp32
			KBUILD_AFLAGS += -mabi=ilp32
			KBUILD_MARCH = rv32im
			LDFLAGS += -melf32lriscv
			endif

			KBUILD_CFLAGS += -Wall

			ifeq ($(CONFIG_RISCV_ISA_A),y)
			KBUILD_ARCH_A = a
			endif
			ifeq ($(CONFIG_RISCV_ISA_C),y)
			KBUILD_ARCH_C = c
			endif

			KBUILD_AFLAGS += -march=$(KBUILD_MARCH)$(KBUILD_ARCH_A)fd$(KBUILD_ARCH_C)

			KBUILD_CFLAGS += -march=$(KBUILD_MARCH)$(KBUILD_ARCH_A)$(KBUILD_ARCH_C)
			KBUILD_CFLAGS += -mno-save-restore
			KBUILD_CFLAGS += -DCONFIG_PAGE_OFFSET=$(CONFIG_PAGE_OFFSET)

			ifeq ($(CONFIG_CMODEL_MEDLOW),y)
			KBUILD_CFLAGS += -mcmodel=medlow
			endif
			ifeq ($(CONFIG_CMODEL_MEDANY),y)
			KBUILD_CFLAGS += -mcmodel=medany
			endif

			# GCC versions that support the "-mstrict-align" option default to allowing
			# unaligned accesses. While unaligned accesses are explicitly allowed in the
			# RISC-V ISA, they're emulated by machine mode traps on all extant
			# architectures. It's faster to have GCC emit only aligned accesses.
			KBUILD_CFLAGS += $(call cc-option,-mstrict-align)

			head-y := arch/riscv/kernel/head.o

			core-y += arch/riscv/kernel/ arch/riscv/mm/

			libs-y += arch/riscv/lib/

			all: vmlinux