Loading arch/arm64/boot/dts/qcom/sm8150-npu.dtsi +8 −31 Original line number Diff line number Diff line Loading @@ -78,29 +78,6 @@ initial-pwrlevel = <4>; qcom,npu-pwrlevel@0 { reg = <0>; clk-freq = <9600000 19200000 19200000 19200000 19200000 9600000 60000000 19200000 19200000 30000000 19200000 19200000 19200000 19200000 9600000 19200000 0 0 0 0>; }; qcom,npu-pwrlevel@1 { reg = <1>; clk-freq = <300000000 19200000 100000000 Loading @@ -122,8 +99,8 @@ 0 0>; }; qcom,npu-pwrlevel@2 { reg = <2>; qcom,npu-pwrlevel@1 { reg = <1>; clk-freq = <350000000 19200000 150000000 Loading @@ -145,8 +122,8 @@ 0 0>; }; qcom,npu-pwrlevel@3 { reg = <3>; qcom,npu-pwrlevel@2 { reg = <2>; clk-freq = <400000000 19200000 200000000 Loading @@ -168,8 +145,8 @@ 0 0>; }; qcom,npu-pwrlevel@4 { reg = <4>; qcom,npu-pwrlevel@3 { reg = <3>; clk-freq = <600000000 19200000 300000000 Loading @@ -191,8 +168,8 @@ 0 0>; }; qcom,npu-pwrlevel@5 { reg = <5>; qcom,npu-pwrlevel@4 { reg = <4>; clk-freq = <715000000 19200000 350000000 Loading drivers/media/platform/msm/npu/npu_common.h +1 −1 Original line number Diff line number Diff line Loading @@ -46,7 +46,7 @@ #define NUM_TOTAL_CLKS 20 #define NPU_MAX_REGULATOR_NUM 2 #define NPU_MAX_DT_NAME_LEN 21 #define NPU_MAX_PWRLEVELS 7 #define NPU_MAX_PWRLEVELS 8 /* ------------------------------------------------------------------------- * Data Structures Loading drivers/media/platform/msm/npu/npu_dev.c +4 −10 Original line number Diff line number Diff line Loading @@ -41,10 +41,6 @@ #define PERF_MODE_DEFAULT 0 #define POWER_LEVEL_MIN_SVS 0 #define POWER_LEVEL_LOW_SVS 1 #define POWER_LEVEL_NOMINAL 4 /* ------------------------------------------------------------------------- * File Scope Prototypes * ------------------------------------------------------------------------- Loading Loading @@ -364,11 +360,6 @@ static uint32_t npu_calc_power_level(struct npu_device *npu_dev) else ret_level = therm_pwr_level; /* adjust the power level */ /* force to lowsvs, minsvs not supported */ if (ret_level == POWER_LEVEL_MIN_SVS) ret_level = POWER_LEVEL_LOW_SVS; pr_debug("%s therm=%d active=%d uc=%d set level=%d\n", __func__, therm_pwr_level, active_pwr_level, uc_pwr_level, ret_level); Loading Loading @@ -432,10 +423,13 @@ int npu_set_uc_power_level(struct npu_device *npu_dev, struct npu_pwrctrl *pwr = &npu_dev->pwrctrl; if (perf_mode == PERF_MODE_DEFAULT) pwr->uc_pwrlevel = POWER_LEVEL_NOMINAL; pwr->uc_pwrlevel = pwr->default_pwrlevel; else pwr->uc_pwrlevel = perf_mode - 1; if (pwr->uc_pwrlevel > pwr->max_pwrlevel) pwr->uc_pwrlevel = pwr->max_pwrlevel; return npu_set_power_level(npu_dev); } Loading Loading
arch/arm64/boot/dts/qcom/sm8150-npu.dtsi +8 −31 Original line number Diff line number Diff line Loading @@ -78,29 +78,6 @@ initial-pwrlevel = <4>; qcom,npu-pwrlevel@0 { reg = <0>; clk-freq = <9600000 19200000 19200000 19200000 19200000 9600000 60000000 19200000 19200000 30000000 19200000 19200000 19200000 19200000 9600000 19200000 0 0 0 0>; }; qcom,npu-pwrlevel@1 { reg = <1>; clk-freq = <300000000 19200000 100000000 Loading @@ -122,8 +99,8 @@ 0 0>; }; qcom,npu-pwrlevel@2 { reg = <2>; qcom,npu-pwrlevel@1 { reg = <1>; clk-freq = <350000000 19200000 150000000 Loading @@ -145,8 +122,8 @@ 0 0>; }; qcom,npu-pwrlevel@3 { reg = <3>; qcom,npu-pwrlevel@2 { reg = <2>; clk-freq = <400000000 19200000 200000000 Loading @@ -168,8 +145,8 @@ 0 0>; }; qcom,npu-pwrlevel@4 { reg = <4>; qcom,npu-pwrlevel@3 { reg = <3>; clk-freq = <600000000 19200000 300000000 Loading @@ -191,8 +168,8 @@ 0 0>; }; qcom,npu-pwrlevel@5 { reg = <5>; qcom,npu-pwrlevel@4 { reg = <4>; clk-freq = <715000000 19200000 350000000 Loading
drivers/media/platform/msm/npu/npu_common.h +1 −1 Original line number Diff line number Diff line Loading @@ -46,7 +46,7 @@ #define NUM_TOTAL_CLKS 20 #define NPU_MAX_REGULATOR_NUM 2 #define NPU_MAX_DT_NAME_LEN 21 #define NPU_MAX_PWRLEVELS 7 #define NPU_MAX_PWRLEVELS 8 /* ------------------------------------------------------------------------- * Data Structures Loading
drivers/media/platform/msm/npu/npu_dev.c +4 −10 Original line number Diff line number Diff line Loading @@ -41,10 +41,6 @@ #define PERF_MODE_DEFAULT 0 #define POWER_LEVEL_MIN_SVS 0 #define POWER_LEVEL_LOW_SVS 1 #define POWER_LEVEL_NOMINAL 4 /* ------------------------------------------------------------------------- * File Scope Prototypes * ------------------------------------------------------------------------- Loading Loading @@ -364,11 +360,6 @@ static uint32_t npu_calc_power_level(struct npu_device *npu_dev) else ret_level = therm_pwr_level; /* adjust the power level */ /* force to lowsvs, minsvs not supported */ if (ret_level == POWER_LEVEL_MIN_SVS) ret_level = POWER_LEVEL_LOW_SVS; pr_debug("%s therm=%d active=%d uc=%d set level=%d\n", __func__, therm_pwr_level, active_pwr_level, uc_pwr_level, ret_level); Loading Loading @@ -432,10 +423,13 @@ int npu_set_uc_power_level(struct npu_device *npu_dev, struct npu_pwrctrl *pwr = &npu_dev->pwrctrl; if (perf_mode == PERF_MODE_DEFAULT) pwr->uc_pwrlevel = POWER_LEVEL_NOMINAL; pwr->uc_pwrlevel = pwr->default_pwrlevel; else pwr->uc_pwrlevel = perf_mode - 1; if (pwr->uc_pwrlevel > pwr->max_pwrlevel) pwr->uc_pwrlevel = pwr->max_pwrlevel; return npu_set_power_level(npu_dev); } Loading