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Commit b14c619e authored by Ashish Kori's avatar Ashish Kori
Browse files

ARM: dts: msm: Add core/core2x clk for SSC QUP 



Add core/core2x clock and SSC QUP sub system name for SA6155,
SA8155 and SA8195 to enable SSR feature and add status field
to QUP node.

Change-Id: I7b198c4eb7bcd7347a879b359a9290e4dc7f97b5
Signed-off-by: default avatarAshish Kori <akori@codeaurora.org>
parent d195d549

arch/arm64/boot/dts/qcom/sa6155-adp-air.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -13,6 +13,10 @@ 
#include <dt-bindings/clock/qcom,gcc-sm6150.h>

#include "sa6155-cnss.dtsi"



&qupv3_2 {

	status = "ok";

};



&bluetooth_ext {

	status = "ok";

};

arch/arm64/boot/dts/qcom/sa6155-adp-star.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -13,6 +13,10 @@ 
#include <dt-bindings/clock/qcom,gcc-sm6150.h>

#include "sa6155-cnss.dtsi"



&qupv3_2 {

	status = "ok";

};



&bluetooth_ext {

	status = "ok";

};

arch/arm64/boot/dts/qcom/sa8155-adp-common.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -16,6 +16,10 @@ 
#include "sa8155-pmic-overlay.dtsi"

#include "sa8155-cnss.dtsi"



&qupv3_3 {

	status = "ok";

};



&qupv3_se0_spi {

	status = "ok";

arch/arm64/boot/dts/qcom/sa8195p-adp-common.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -14,6 +14,10 @@ 
#include <dt-bindings/input/input.h>

#include "sa8195p-cnss.dtsi"



&qupv3_3 {

	status = "ok";

};



&qupv3_se0_spi {

	status = "ok";

arch/arm64/boot/dts/qcom/sdmshrike-qupv3.dtsi

+9 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -29,6 +29,7 @@ 
		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_0>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,iommu-s1-bypass;

		status = "ok";



		iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";
@@ -348,6 +349,7 @@ 
		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_1>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,iommu-s1-bypass;

		status = "ok";



		iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";
@@ -616,6 +618,7 @@ 
		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_2>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,iommu-s1-bypass;

		status = "ok";



		iommu_qupv3_2_geni_se_cb: qcom,iommu_qupv3_2_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";
@@ -871,6 +874,11 @@ 
		qcom,bus-mas-id = <MSM_BUS_MASTER_SENSORS_AHB>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,iommu-s1-bypass;

		qcom,subsys-name = "slpi";

		clock-names = "corex", "core2x";

		clocks = <&clock_scc SCC_QUPV3_CORE_CLK>,

			<&clock_scc SCC_QUPV3_2XCORE_CLK>;

		status = "disabled";



		iommu_qupv3_3_geni_se_cb: qcom,iommu_qupv3_3_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";