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Commit b0e7031a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://github.com/davem330/net 

* git://github.com/davem330/net: (62 commits)
  ipv6: don't use inetpeer to store metrics for routes.
  can: ti_hecc: include linux/io.h
  IRDA: Fix global type conflicts in net/irda/irsysctl.c v2
  net: Handle different key sizes between address families in flow cache
  net: Align AF-specific flowi structs to long
  ipv4: Fix fib_info->fib_metrics leak
  caif: fix a potential NULL dereference
  sctp: deal with multiple COOKIE_ECHO chunks
  ibmveth: Fix checksum offload failure handling
  ibmveth: Checksum offload is always disabled
  ibmveth: Fix issue with DMA mapping failure
  ibmveth: Fix DMA unmap error
  pch_gbe: support ML7831 IOH
  pch_gbe: added the process of FIFO over run error
  pch_gbe: fixed the issue which receives an unnecessary packet.
  sfc: Use 64-bit writes for TX push where possible
  Revert "sfc: Use write-combining to reduce TX latency" and follow-ups
  bnx2x: Fix ethtool advertisement
  bnx2x: Fix 578xx link LED
  bnx2x: Fix XMAC loopback test
  ...
parents 01a71435 8e2ec639

Documentation/networking/dmfe.txt

+2 −1
Original line number Diff line number Diff line 
Note: This driver doesn't have a maintainer.



Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver for Linux.



This program is free software; you can redistribute it and/or
@@ -55,7 +57,6 @@ Test and make sure PCI latency is now correct for all cases. 
Authors:



Sten Wang <sten_wang@davicom.com.tw >   : Original Author

Tobias Ringstrom <tori@unhappy.mine.nu> : Current Maintainer



Contributors:

MAINTAINERS

+2 −4
Original line number Diff line number Diff line
@@ -1278,7 +1278,6 @@ F: drivers/input/misc/ati_remote2.c 
ATLX ETHERNET DRIVERS

M:	Jay Cliburn <jcliburn@gmail.com>

M:	Chris Snook <chris.snook@gmail.com>

M:	Jie Yang <jie.yang@atheros.com>

L:	netdev@vger.kernel.org

W:	http://sourceforge.net/projects/atl1

W:	http://atl1.sourceforge.net
@@ -1574,7 +1573,6 @@ F: drivers/scsi/bfa/ 


BROCADE BNA 10 GIGABIT ETHERNET DRIVER

M:	Rasesh Mody <rmody@brocade.com>

M:	Debashis Dutt <ddutt@brocade.com>

L:	netdev@vger.kernel.org

S:	Supported

F:	drivers/net/bna/
@@ -1758,7 +1756,6 @@ F: Documentation/zh_CN/ 


CISCO VIC ETHERNET NIC DRIVER

M:	Christian Benvenuti <benve@cisco.com>

M:	Vasanthy Kolluri <vkolluri@cisco.com>

M:	Roopa Prabhu <roprabhu@cisco.com>

M:	David Wang <dwang2@cisco.com>

S:	Supported
@@ -4415,7 +4412,8 @@ L: netfilter@vger.kernel.org 
L:	coreteam@netfilter.org

W:	http://www.netfilter.org/

W:	http://www.iptables.org/

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/kaber/nf-2.6.git

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf-2.6.git

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf-next-2.6.git

S:	Supported

F:	include/linux/netfilter*

F:	include/linux/netfilter/

drivers/net/Kconfig

+6 −5
Original line number Diff line number Diff line
@@ -2535,7 +2535,7 @@ config S6GMAC 
source "drivers/net/stmmac/Kconfig"



config PCH_GBE

	tristate "Intel EG20T PCH / OKI SEMICONDUCTOR ML7223 IOH GbE"

	tristate "Intel EG20T PCH/OKI SEMICONDUCTOR IOH(ML7223/ML7831) GbE"

	depends on PCI

	select MII

	---help---
@@ -2548,10 +2548,11 @@ config PCH_GBE 
	  This driver enables Gigabit Ethernet function.



	  This driver also can be used for OKI SEMICONDUCTOR IOH(Input/

	  Output Hub), ML7223.

	  ML7223 IOH is for MP(Media Phone) use.

	  ML7223 is companion chip for Intel Atom E6xx series.

	  ML7223 is completely compatible for Intel EG20T PCH.

	  Output Hub), ML7223/ML7831.

	  ML7223 IOH is for MP(Media Phone) use. ML7831 IOH is for general

	  purpose use.

	  ML7223/ML7831 is companion chip for Intel Atom E6xx series.

	  ML7223/ML7831 is completely compatible for Intel EG20T PCH.



config FTGMAC100

	tristate "Faraday FTGMAC100 Gigabit Ethernet support"

drivers/net/bnx2x/bnx2x.h

+92 −32
Original line number Diff line number Diff line
@@ -315,6 +315,14 @@ union db_prod { 
	u32		raw;

};



/* dropless fc FW/HW related params */

#define BRB_SIZE(bp)		(CHIP_IS_E3(bp) ? 1024 : 512)

#define MAX_AGG_QS(bp)		(CHIP_IS_E1(bp) ? \

					ETH_MAX_AGGREGATION_QUEUES_E1 :\

					ETH_MAX_AGGREGATION_QUEUES_E1H_E2)

#define FW_DROP_LEVEL(bp)	(3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))

#define FW_PREFETCH_CNT		16

#define DROPLESS_FC_HEADROOM	100



/* MC hsi */

#define BCM_PAGE_SHIFT		12
@@ -331,15 +339,35 @@ union db_prod { 
/* SGE ring related macros */

#define NUM_RX_SGE_PAGES	2

#define RX_SGE_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))

#define MAX_RX_SGE_CNT		(RX_SGE_CNT - 2)

#define NEXT_PAGE_SGE_DESC_CNT	2

#define MAX_RX_SGE_CNT		(RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)

/* RX_SGE_CNT is promised to be a power of 2 */

#define RX_SGE_MASK		(RX_SGE_CNT - 1)

#define NUM_RX_SGE		(RX_SGE_CNT * NUM_RX_SGE_PAGES)

#define MAX_RX_SGE		(NUM_RX_SGE - 1)

#define NEXT_SGE_IDX(x)		((((x) & RX_SGE_MASK) == \

				  (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)

				  (MAX_RX_SGE_CNT - 1)) ? \

					(x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \

					(x) + 1)

#define RX_SGE(x)		((x) & MAX_RX_SGE)



/*

 * Number of required  SGEs is the sum of two:

 * 1. Number of possible opened aggregations (next packet for

 *    these aggregations will probably consume SGE immidiatelly)

 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only

 *    after placement on BD for new TPA aggregation)

 *

 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page

 */

#define NUM_SGE_REQ		(MAX_AGG_QS(bp) + \

					(BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)

#define NUM_SGE_PG_REQ		((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \

						MAX_RX_SGE_CNT)

#define SGE_TH_LO(bp)		(NUM_SGE_REQ + \

				 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)

#define SGE_TH_HI(bp)		(SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)



/* Manipulate a bit vector defined as an array of u64 */



/* Number of bits in one sge_mask array element */
@@ -551,24 +579,43 @@ struct bnx2x_fastpath { 


#define NUM_TX_RINGS		16

#define TX_DESC_CNT		(BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))

#define MAX_TX_DESC_CNT		(TX_DESC_CNT - 1)

#define NEXT_PAGE_TX_DESC_CNT	1

#define MAX_TX_DESC_CNT		(TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)

#define NUM_TX_BD		(TX_DESC_CNT * NUM_TX_RINGS)

#define MAX_TX_BD		(NUM_TX_BD - 1)

#define MAX_TX_AVAIL		(MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)

#define NEXT_TX_IDX(x)		((((x) & MAX_TX_DESC_CNT) == \

				  (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)

				  (MAX_TX_DESC_CNT - 1)) ? \

					(x) + 1 + NEXT_PAGE_TX_DESC_CNT : \

					(x) + 1)

#define TX_BD(x)		((x) & MAX_TX_BD)

#define TX_BD_POFF(x)		((x) & MAX_TX_DESC_CNT)



/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */

#define NUM_RX_RINGS		8

#define RX_DESC_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))

#define MAX_RX_DESC_CNT		(RX_DESC_CNT - 2)

#define NEXT_PAGE_RX_DESC_CNT	2

#define MAX_RX_DESC_CNT		(RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)

#define RX_DESC_MASK		(RX_DESC_CNT - 1)

#define NUM_RX_BD		(RX_DESC_CNT * NUM_RX_RINGS)

#define MAX_RX_BD		(NUM_RX_BD - 1)

#define MAX_RX_AVAIL		(MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)

#define MIN_RX_AVAIL		128



/* dropless fc calculations for BDs

 *

 * Number of BDs should as number of buffers in BRB:

 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT

 * "next" elements on each page

 */

#define NUM_BD_REQ		BRB_SIZE(bp)

#define NUM_BD_PG_REQ		((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \

					      MAX_RX_DESC_CNT)

#define BD_TH_LO(bp)		(NUM_BD_REQ + \

				 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \

				 FW_DROP_LEVEL(bp))

#define BD_TH_HI(bp)		(BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)



#define MIN_RX_AVAIL		((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)



#define MIN_RX_SIZE_TPA_HW	(CHIP_IS_E1(bp) ? \

					ETH_MIN_RX_CQES_WITH_TPA_E1 : \
@@ -579,7 +626,9 @@ struct bnx2x_fastpath { 
								MIN_RX_AVAIL))



#define NEXT_RX_IDX(x)		((((x) & RX_DESC_MASK) == \

				  (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)

				  (MAX_RX_DESC_CNT - 1)) ? \

					(x) + 1 + NEXT_PAGE_RX_DESC_CNT : \

					(x) + 1)

#define RX_BD(x)		((x) & MAX_RX_BD)



/*
@@ -589,14 +638,31 @@ struct bnx2x_fastpath { 
#define CQE_BD_REL	(sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))

#define NUM_RCQ_RINGS		(NUM_RX_RINGS * CQE_BD_REL)

#define RCQ_DESC_CNT		(BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))

#define MAX_RCQ_DESC_CNT	(RCQ_DESC_CNT - 1)

#define NEXT_PAGE_RCQ_DESC_CNT	1

#define MAX_RCQ_DESC_CNT	(RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)

#define NUM_RCQ_BD		(RCQ_DESC_CNT * NUM_RCQ_RINGS)

#define MAX_RCQ_BD		(NUM_RCQ_BD - 1)

#define MAX_RCQ_AVAIL		(MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)

#define NEXT_RCQ_IDX(x)		((((x) & MAX_RCQ_DESC_CNT) == \

				  (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)

				  (MAX_RCQ_DESC_CNT - 1)) ? \

					(x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \

					(x) + 1)

#define RCQ_BD(x)		((x) & MAX_RCQ_BD)



/* dropless fc calculations for RCQs

 *

 * Number of RCQs should be as number of buffers in BRB:

 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT

 * "next" elements on each page

 */

#define NUM_RCQ_REQ		BRB_SIZE(bp)

#define NUM_RCQ_PG_REQ		((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \

					      MAX_RCQ_DESC_CNT)

#define RCQ_TH_LO(bp)		(NUM_RCQ_REQ + \

				 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \

				 FW_DROP_LEVEL(bp))

#define RCQ_TH_HI(bp)		(RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)





/* This is needed for determining of last_max */

#define SUB_S16(a, b)		(s16)((s16)(a) - (s16)(b))
@@ -685,24 +751,17 @@ struct bnx2x_fastpath { 
#define FP_CSB_FUNC_OFF	\

			offsetof(struct cstorm_status_block_c, func)



#define HC_INDEX_TOE_RX_CQ_CONS		0 /* Formerly Ustorm TOE CQ index */

					  /* (HC_INDEX_U_TOE_RX_CQ_CONS)  */

#define HC_INDEX_ETH_RX_CQ_CONS		1 /* Formerly Ustorm ETH CQ index */

					  /* (HC_INDEX_U_ETH_RX_CQ_CONS)  */

#define HC_INDEX_ETH_RX_BD_CONS		2 /* Formerly Ustorm ETH BD index */

					  /* (HC_INDEX_U_ETH_RX_BD_CONS)  */



#define HC_INDEX_TOE_TX_CQ_CONS		4 /* Formerly Cstorm TOE CQ index   */

					  /* (HC_INDEX_C_TOE_TX_CQ_CONS)    */

#define HC_INDEX_ETH_TX_CQ_CONS_COS0	5 /* Formerly Cstorm ETH CQ index   */

					  /* (HC_INDEX_C_ETH_TX_CQ_CONS)    */

#define HC_INDEX_ETH_TX_CQ_CONS_COS1	6 /* Formerly Cstorm ETH CQ index   */

					  /* (HC_INDEX_C_ETH_TX_CQ_CONS)    */

#define HC_INDEX_ETH_TX_CQ_CONS_COS2	7 /* Formerly Cstorm ETH CQ index   */

					  /* (HC_INDEX_C_ETH_TX_CQ_CONS)    */

#define HC_INDEX_ETH_RX_CQ_CONS		1



#define HC_INDEX_ETH_FIRST_TX_CQ_CONS	HC_INDEX_ETH_TX_CQ_CONS_COS0

#define HC_INDEX_OOO_TX_CQ_CONS		4



#define HC_INDEX_ETH_TX_CQ_CONS_COS0	5



#define HC_INDEX_ETH_TX_CQ_CONS_COS1	6



#define HC_INDEX_ETH_TX_CQ_CONS_COS2	7



#define HC_INDEX_ETH_FIRST_TX_CQ_CONS	HC_INDEX_ETH_TX_CQ_CONS_COS0



#define BNX2X_RX_SB_INDEX \

	(&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
@@ -1100,11 +1159,12 @@ struct bnx2x { 
#define BP_PORT(bp)			(bp->pfid & 1)

#define BP_FUNC(bp)			(bp->pfid)

#define BP_ABS_FUNC(bp)			(bp->pf_num)

#define BP_E1HVN(bp)			(bp->pfid >> 1)

#define BP_VN(bp)			(BP_E1HVN(bp)) /*remove when approved*/

#define BP_L_ID(bp)			(BP_E1HVN(bp) << 2)

#define BP_FW_MB_IDX(bp)		(BP_PORT(bp) +\

	  BP_VN(bp) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2  : 1))

#define BP_VN(bp)			((bp)->pfid >> 1)

#define BP_MAX_VN_NUM(bp)		(CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)

#define BP_L_ID(bp)			(BP_VN(bp) << 2)

#define BP_FW_MB_IDX_VN(bp, vn)		(BP_PORT(bp) +\

	  (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2  : 1))

#define BP_FW_MB_IDX(bp)		BP_FW_MB_IDX_VN(bp, BP_VN(bp))



	struct net_device	*dev;

	struct pci_dev		*pdev;
@@ -1767,7 +1827,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 


#define MAX_DMAE_C_PER_PORT		8

#define INIT_DMAE_C(bp)			(BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \

					 BP_E1HVN(bp))

					 BP_VN(bp))

#define PMF_DMAE_C(bp)			(BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \

					 E1HVN_MAX)
@@ -1793,7 +1853,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 


/* must be used on a CID before placing it on a HW ring */

#define HW_CID(bp, x)			((BP_PORT(bp) << 23) | \

					 (BP_E1HVN(bp) << BNX2X_SWCID_SHIFT) | \

					 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \

					 (x))



#define SP_DESC_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_spe))

drivers/net/bnx2x/bnx2x_cmn.c

+14 −13
Original line number Diff line number Diff line
@@ -987,8 +987,6 @@ void __bnx2x_link_report(struct bnx2x *bp) 
void bnx2x_init_rx_rings(struct bnx2x *bp)

{

	int func = BP_FUNC(bp);

	int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :

					      ETH_MAX_AGGREGATION_QUEUES_E1H_E2;

	u16 ring_prod;

	int i, j;
@@ -1001,7 +999,7 @@ void bnx2x_init_rx_rings(struct bnx2x *bp) 


		if (!fp->disable_tpa) {

			/* Fill the per-aggregtion pool */

			for (i = 0; i < max_agg_queues; i++) {

			for (i = 0; i < MAX_AGG_QS(bp); i++) {

				struct bnx2x_agg_info *tpa_info =

					&fp->tpa_info[i];

				struct sw_rx_bd *first_buf =
@@ -1041,7 +1039,7 @@ void bnx2x_init_rx_rings(struct bnx2x *bp) 
					bnx2x_free_rx_sge_range(bp, fp,

								ring_prod);

					bnx2x_free_tpa_pool(bp, fp,

							    max_agg_queues);

							    MAX_AGG_QS(bp));

					fp->disable_tpa = 1;

					ring_prod = 0;

					break;
@@ -1137,9 +1135,7 @@ static void bnx2x_free_rx_skbs(struct bnx2x *bp) 
		bnx2x_free_rx_bds(fp);



		if (!fp->disable_tpa)

			bnx2x_free_tpa_pool(bp, fp, CHIP_IS_E1(bp) ?

					    ETH_MAX_AGGREGATION_QUEUES_E1 :

					    ETH_MAX_AGGREGATION_QUEUES_E1H_E2);

			bnx2x_free_tpa_pool(bp, fp, MAX_AGG_QS(bp));

	}

}
@@ -3095,15 +3091,20 @@ static int bnx2x_alloc_fp_mem_at(struct bnx2x *bp, int index) 
	struct bnx2x_fastpath *fp = &bp->fp[index];

	int ring_size = 0;

	u8 cos;

	int rx_ring_size = 0;



	/* if rx_ring_size specified - use it */

	int rx_ring_size = bp->rx_ring_size ? bp->rx_ring_size :

			   MAX_RX_AVAIL/BNX2X_NUM_RX_QUEUES(bp);

	if (!bp->rx_ring_size) {



		rx_ring_size = MAX_RX_AVAIL/BNX2X_NUM_RX_QUEUES(bp);



		/* allocate at least number of buffers required by FW */

		rx_ring_size = max_t(int, bp->disable_tpa ? MIN_RX_SIZE_NONTPA :

						    MIN_RX_SIZE_TPA,

				  rx_ring_size);

				     MIN_RX_SIZE_TPA, rx_ring_size);



		bp->rx_ring_size = rx_ring_size;

	} else

		rx_ring_size = bp->rx_ring_size;



	/* Common */

	sb = &bnx2x_fp(bp, index, status_blk);