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Commit b0c1bbcb authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "Merge remote-tracking branch 'quic/dev/msm-4.14-display' into msm-4.14"

parents e0f33892 11f666ed

Documentation/devicetree/bindings/drm/msm/sde-dsi.txt

+1 −0
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@@ -83,6 +83,7 @@ Optional properties: 
					-- qcom,supply-max-voltage: maximum voltage level (uV)

					-- qcom,supply-enable-load: load drawn (uA) from enabled supply

					-- qcom,supply-disable-load: load drawn (uA) from disabled supply

					-- qcom,supply-off-min-voltage: minimum voltage level (uV) when turned off

					-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on

					-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on

					-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off

Documentation/devicetree/bindings/drm/msm/sde-shd.txt

0 → 100644
+101 −0
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QTI Snapdragon Display Engine (SDE) shared display



Required properties:

- compatible:		"qcom,shared-display"

- qcom,shared-display-base: node handle of qcom,shared-display-base, see below.

- qcom,blend-stage-range: A pair of u32 property <start size> defines the blend

			stage start and size for the shared display. For example

			<4 5> indicates this shared display's blending stage starts

			from 4 and there are 5 stages in total. Different shared

			display located on the same base display should not overlap

			with their blend stages. The maximum stages should be within

			the range of layer mixer hardware capability.

- qcom,shared-display-src-mode: source resolution of the shared display, which is also

			the framebuffer size. It contains two properties:

			qcom,mode-h-active: A u32 property defines horizontal resolution.

			qcom,mode-v-active: A u32 property defines vertical resolution.

- qcom,shared-display-dst-mode: destination rectangle in the shared display, which also

			includes the padding lines if line padding feature is enabled.

			It contains 4 properties:

			qcom,mode-x-offset: A u32 property of x offset.

			qcom,mode-y-offset: A u32 property of y offset.

			qcom,mode-width: A u32 property of width.

			qcom,mode-height: A u32 property of height, including line padding.





qcom,shared-display-base properties:

- qcom,shared-display-base-intf: A u32 property defines intf index of the base display.

- qcom,shared-display-base-mst: A u32 property defines the DP MST branch port, needed if

			the base display sits on DP MST display.

- qcom,shared-display-base-mode: timing of the physical base display, contains the

			following properties:

			qcom,mode-h-active: A u32 property defines the horizontal active size.

			qcom,mode-h-front-porch: A u32 property defines the horizontal front porch.

			qcom,mode-h-pulse-width: A u32 property defines the horizontal pulse.

			qcom,mode-h-back-porch: A u32 property defines the horizontal back porch.

			qcom,mode-h-active-high: A boolean property defines if horizontal polarity

						is high.

			qcom,mode-v-active: A u32 property defines the vertical active size.

			qcom,mode-v-front-porch: A u32 property defines the vertical front portch.

			qcom,mode-v-pulse-width: A u32 property defines the vertical pulse width.

			qcom,mode-v-back-porch: A u32 property defines the vertical back porch.

			qcom,mode-v-active-high: A boolean property defines if vertical polarity

						is high.

			qcom,mode-refresh-rate: A u32 property defines vertial refresh rate.

			qcom,mode-clock-in-khz: A u32 property defines clock in kHz.



Example:



/ {

	...



	sde_sh_base0: qcom,shared-display-base@0 {

		qcom,shared-display-base-intf = <0>;

		qcom,shared-display-base-mode {

			qcom,mode-h-active = <3840>;

			qcom,mode-h-front-porch = <176>;

			qcom,mode-h-pulse-width = <88>;

			qcom,mode-h-back-porch = <296>;

			qcom,mode-h-active-high;

			qcom,mode-v-active = <2160>;

			qcom,mode-v-front-porch = <8>;

			qcom,mode-v-pulse-width = <10>;

			qcom,mode-v-back-porch = <72>;

			qcom,mode-v-active-high;

			qcom,mode-refresh-rate = <30>;

			qcom,mode-clock-in-khz = <297000>;

		};

	};



	sde_sh0: qcom,shared-display@0 {

		compatible = "qcom,shared-display";

		qcom,shared-display-base = <&sde_sh_base0>;

		qcom,blend-stage-range = <0 5>;

		qcom,shared-display-src-mode {

			qcom,mode-h-active = <1920>;

			qcom,mode-v-active = <2160>;

		};

		qcom,shared-display-dst-mode {

			qcom,mode-x-offset = <0>;

			qcom,mode-y-offset = <0>;

			qcom,mode-width = <1920>;

			qcom,mode-height = <2160>;

		};

	};



	sde_sh1: qcom,shared-display@1 {

		compatible = "qcom,shared-display";

		qcom,shared-display-base = <&sde_sh_base0>;

		qcom,blend-stage-range = <5 5>;

		qcom,shared-display-src-mode {

			qcom,mode-h-active = <1920>;

			qcom,mode-v-active = <2160>;

		};

		qcom,shared-display-dst-mode {

			qcom,mode-x-offset = <1920>;

			qcom,mode-y-offset = <0>;

			qcom,mode-width = <1920>;

			qcom,mode-height = <2160>;

		};

	};

};

drivers/clk/qcom/mdss/mdss-dsi-pll-14nm-util.c

+1 −1
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@@ -1145,7 +1145,7 @@ void pll_vco_unprepare_14nm(struct clk_hw *hw) 
		return;

	}



	pll->vco_cached_rate = clk_hw_get_rate(hw);

	pll->vco_cached_rate = clk_get_rate(hw->clk);

	dsi_pll_disable(hw);

}

drivers/clk/qcom/mdss/mdss-dsi-pll-14nm.c

+4 −0
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ static struct dsi_pll_vco_clk dsi0pll_vco_clk = { 
			.name = "dsi0pll_vco_clk_14nm",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_ops_dsi_vco,

		},

};
@@ -92,6 +93,7 @@ static struct dsi_pll_vco_clk dsi0pll_shadow_vco_clk = { 
			.name = "dsi0pll_shadow_vco_clk_14nm",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_ops_shadow_dsi_vco,

		},

};
@@ -106,6 +108,7 @@ static struct dsi_pll_vco_clk dsi1pll_vco_clk = { 
			.name = "dsi1pll_vco_clk_14nm",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_ops_dsi_vco,

		},

};
@@ -120,6 +123,7 @@ static struct dsi_pll_vco_clk dsi1pll_shadow_vco_clk = { 
			.name = "dsi1pll_shadow_vco_clk_14nm",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_ops_shadow_dsi_vco,

		},

};

drivers/gpu/drm/msm/Kconfig

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@@ -152,6 +152,16 @@ config DRM_SDE_WB 
	  the output image is written back to memory in the format

	  selected by the connector's mode and property settings.



config DRM_SDE_SHD

	bool "Enable Shared display support in SDE DRM"

	depends on DRM_MSM

	help

	  Choose this option for shared display support.

	  This option enables multiple logical displays

	  to share one base physical encoder/connector.

	  Each logical display will appear as different

	  connectors and report back to user.



config DRM_MSM_DSI_14NM_PHY

	bool "Enable DSI 14nm PHY driver in MSM DRM (used by MSM8996/APQ8096)"

	depends on DRM_MSM_DSI