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Commit b0b8ac86 authored by Shashank Babu Chinta Venkata's avatar Shashank Babu Chinta Venkata
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drivers: clk: qcom: alter PLL locking sequence for 7nm DSI PHY 



Alter 7nm DSI PHY locking sequence per latest recommendations.

Change-Id: I2f0498d2b0500899af38e7f2948f0f84fef75f3a
Signed-off-by: default avatarShashank Babu Chinta Venkata <sbchin@codeaurora.org>
parent 45d187f6

drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c

+7 −2
Original line number Diff line number Diff line
@@ -590,6 +590,8 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll, 
	void __iomem *pll_base = rsc->pll_base;



	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FIVE_1, 0x01);

	MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00);

	MDSS_PLL_REG_W(pll_base, PLL_GEAR_BAND_SELECT_CONTROLS, 0x21);

	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FIVE, 0x01);

	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_TWO, 0x03);

	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_THREE, 0x00);
@@ -601,11 +603,15 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll, 
	MDSS_PLL_REG_W(pll_base, PLL_OUTDIV, 0x00);

	MDSS_PLL_REG_W(pll_base, PLL_CORE_OVERRIDE, 0x00);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_PROP_GAIN_RATE_1, 0x08);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_PROP_GAIN_RATE_1, 0x0a);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_BAND_SEL_RATE_1, 0xc0);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_OVERRIDE, 0x80);

	MDSS_PLL_REG_W(pll_base, PLL_PFILT, 0x29);

	MDSS_PLL_REG_W(pll_base, PLL_PFILT, 0x2f);

	MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x2a);

	MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x3f);

}
@@ -766,7 +772,6 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll, 
	MDSS_PLL_REG_W(pll_base, PLL_CMODE_1, 0x10);

	MDSS_PLL_REG_W(pll_base, PLL_CLOCK_INVERTERS_1,

			reg->pll_clock_inverters);



}



static int vco_7nm_set_rate(struct clk_hw *hw, unsigned long rate,