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Commit af4fa29b authored by David Dai's avatar David Dai Committed by Gerrit - the friendly Code Review server
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clk: qcom: Add bw voting ops for clk-alpha-pll and rcg 



Add callbacks to vote for bandwidth for the sake of accessing
multimedia clock controllers to clock operators.

Change-Id: I4b911deadaa9d8fd5a79b9b0bf68fa38e7172719
Signed-off-by: default avatarDavid Dai <daidavid1@codeaurora.org>
parent 5c296134

drivers/clk/qcom/clk-alpha-pll.c

+14 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 


#include "clk-alpha-pll.h"

#include "common.h"

#include "clk-debug.h"



#define PLL_MODE		0x00

#define PLL_OUTCTRL		BIT(0)
@@ -1297,6 +1298,7 @@ const struct clk_ops clk_pll_sleep_vote_ops = { 
	.enable = clk_enable_regmap,

	.disable = clk_disable_regmap,

	.list_registers = clk_alpha_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL(clk_pll_sleep_vote_ops);
@@ -1308,6 +1310,7 @@ const struct clk_ops clk_alpha_pll_ops = { 
	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_alpha_pll_set_rate,

	.list_registers = clk_alpha_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
@@ -1319,6 +1322,7 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = { 
	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_alpha_pll_set_rate,

	.list_registers = clk_alpha_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
@@ -1331,6 +1335,7 @@ const struct clk_ops clk_trion_pll_ops = { 
	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_trion_pll_set_rate,

	.list_registers = clk_trion_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_trion_pll_ops);
@@ -1341,6 +1346,7 @@ const struct clk_ops clk_trion_fixed_pll_ops = { 
	.recalc_rate = clk_trion_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.list_registers = clk_trion_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
@@ -1352,6 +1358,7 @@ const struct clk_ops clk_regera_pll_ops = { 
	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_regera_pll_set_rate,

	.list_registers = clk_regera_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_regera_pll_ops);
@@ -1417,6 +1424,7 @@ const struct clk_ops clk_alpha_pll_postdiv_ops = { 
	.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,

	.round_rate = clk_alpha_pll_postdiv_round_rate,

	.set_rate = clk_alpha_pll_postdiv_set_rate,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
@@ -1498,6 +1506,7 @@ const struct clk_ops clk_trion_pll_postdiv_ops = { 
	.recalc_rate = clk_trion_pll_postdiv_recalc_rate,

	.round_rate = clk_trion_pll_postdiv_round_rate,

	.set_rate = clk_trion_pll_postdiv_set_rate,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_trion_pll_postdiv_ops);
@@ -1704,6 +1713,7 @@ const struct clk_ops clk_alpha_pll_slew_ops = { 
	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_alpha_pll_slew_set_rate,

	.list_registers = clk_alpha_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL(clk_alpha_pll_slew_ops);
@@ -2047,6 +2057,7 @@ const struct clk_ops clk_fabia_pll_ops = { 
	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_fabia_pll_set_rate,

	.list_registers = clk_fabia_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL(clk_fabia_pll_ops);
@@ -2056,6 +2067,7 @@ const struct clk_ops clk_fabia_fixed_pll_ops = { 
	.recalc_rate = clk_fabia_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.list_registers = clk_fabia_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL(clk_fabia_fixed_pll_ops);
@@ -2137,6 +2149,7 @@ const struct clk_ops clk_generic_pll_postdiv_ops = { 
	.recalc_rate = clk_generic_pll_postdiv_recalc_rate,

	.round_rate = clk_generic_pll_postdiv_round_rate,

	.set_rate = clk_generic_pll_postdiv_set_rate,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL(clk_generic_pll_postdiv_ops);
@@ -2274,5 +2287,6 @@ const struct clk_ops clk_agera_pll_ops = { 
	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_agera_pll_set_rate,

	.list_registers = clk_agera_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL(clk_agera_pll_ops);

drivers/clk/qcom/clk-branch.c

+6 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013, 2017, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013, 2017-2018 The Linux Foundation. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and
@@ -189,6 +189,7 @@ const struct clk_ops clk_branch_ops = { 
	.disable = clk_branch_disable,

	.is_enabled = clk_is_enabled_regmap,

	.set_flags = clk_branch_set_flags,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_branch_ops);
@@ -378,6 +379,7 @@ const struct clk_ops clk_branch2_ops = { 
	.set_flags = clk_branch_set_flags,

	.list_registers = clk_branch2_list_registers,

	.debug_init = clk_debug_measure_add,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_branch2_ops);
@@ -443,6 +445,7 @@ const struct clk_ops clk_branch2_hw_ctl_ops = { 
	.recalc_rate = clk_branch2_hw_ctl_recalc_rate,

	.determine_rate = clk_branch2_hw_ctl_determine_rate,

	.set_flags = clk_branch_set_flags,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_branch2_hw_ctl_ops);
@@ -500,6 +503,7 @@ const struct clk_ops clk_gate2_ops = { 
	.is_enabled = clk_is_enabled_regmap,

	.list_registers = clk_gate2_list_registers,

	.debug_init = clk_debug_measure_add,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_gate2_ops);
@@ -507,5 +511,6 @@ const struct clk_ops clk_branch_simple_ops = { 
	.enable = clk_enable_regmap,

	.disable = clk_disable_regmap,

	.is_enabled = clk_is_enabled_regmap,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_branch_simple_ops);

drivers/clk/qcom/clk-debug.c

+6 −0
Original line number Diff line number Diff line
@@ -392,3 +392,9 @@ int clk_debug_measure_register(struct clk_hw *hw) 
}

EXPORT_SYMBOL(clk_debug_measure_register);



void clk_debug_bus_vote(struct clk_hw *hw, bool enable)

{

	if (hw->init->bus_cl_id)

		msm_bus_scale_client_update_request(hw->init->bus_cl_id,

								enable);

}

drivers/clk/qcom/clk-debug.h

+1 −0
Original line number Diff line number Diff line
@@ -140,5 +140,6 @@ extern const struct clk_ops clk_debug_mux_ops; 


int clk_debug_measure_register(struct clk_hw *hw);

int clk_debug_measure_add(struct clk_hw *hw, struct dentry *dentry);

void clk_debug_bus_vote(struct clk_hw *hw, bool enable);



#endif

drivers/clk/qcom/clk-rcg2.c

+10 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 


#include "clk-rcg.h"

#include "common.h"

#include "clk-debug.h"



#define CMD_REG			0x0

#define CMD_UPDATE		BIT(0)
@@ -683,6 +684,7 @@ const struct clk_ops clk_rcg2_ops = { 
	.set_rate_and_parent = clk_rcg2_set_rate_and_parent,

	.list_rate = clk_rcg2_list_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_rcg2_ops);
@@ -696,6 +698,7 @@ const struct clk_ops clk_rcg2_floor_ops = { 
	.set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent,

	.list_rate = clk_rcg2_list_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
@@ -776,6 +779,7 @@ const struct clk_ops clk_rcg2_shared_ops = { 
	.determine_rate = clk_rcg2_determine_rate,

	.set_rate = clk_rcg2_shared_set_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
@@ -904,6 +908,7 @@ const struct clk_ops clk_edp_pixel_ops = { 
	.set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,

	.determine_rate = clk_edp_pixel_determine_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
@@ -963,6 +968,7 @@ const struct clk_ops clk_byte_ops = { 
	.set_rate_and_parent = clk_byte_set_rate_and_parent,

	.determine_rate = clk_byte_determine_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_byte_ops);
@@ -1034,6 +1040,7 @@ const struct clk_ops clk_byte2_ops = { 
	.set_rate_and_parent = clk_byte2_set_rate_and_parent,

	.determine_rate = clk_byte2_determine_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_byte2_ops);
@@ -1126,6 +1133,7 @@ const struct clk_ops clk_pixel_ops = { 
	.set_rate_and_parent = clk_pixel_set_rate_and_parent,

	.determine_rate = clk_pixel_determine_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_pixel_ops);
@@ -1211,6 +1219,7 @@ const struct clk_ops clk_dp_ops = { 
	.set_rate_and_parent = clk_dp_set_rate_and_parent,

	.determine_rate = clk_dp_determine_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_dp_ops);
@@ -1302,6 +1311,7 @@ const struct clk_ops clk_gfx3d_ops = { 
	.set_rate_and_parent = clk_gfx3d_set_rate_and_parent,

	.determine_rate = clk_gfx3d_determine_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_gfx3d_ops);