Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit aea4b707 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge changes I8af751ea,I2f0498d2,I96e112f8 into msm-4.14 

* changes:
  drm/msm/dsi-staging: alter 7nm PHY enable sequence for DSI
  drivers: clk: qcom: alter PLL locking sequence for 7nm DSI PHY
  ARM: dts: msm: alter DSI PHY lane configurations for SDM855
parents 9be67373 89629835

arch/arm64/boot/dts/qcom/sdm855-sde.dtsi

+10 −10
Original line number Diff line number Diff line
@@ -552,11 +552,11 @@ 
						55 03

						55 03

						55 00];

		qcom,platform-lane-config = [00 00 00 00

						00 00 00 00

						00 00 00 00

						00 00 00 00

						00 00 00 80];

		qcom,platform-lane-config = [00 00 0a 0a

						00 00 0a 0a

						00 00 0a 0a

						00 00 0a 0a

						00 00 8a 8a];

		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];

		qcom,phy-supply-entries {

			#address-cells = <1>;
@@ -585,11 +585,11 @@ 
						55 03

						55 00];

		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];

		qcom,platform-lane-config = [00 00 00 00

						00 00 00 00

						00 00 00 00

						00 00 00 00

						00 00 00 80];

		qcom,platform-lane-config = [00 00 0a 0a

						00 00 0a 0a

						00 00 0a 0a

						00 00 0a 0a

						00 00 8a 8a];

		qcom,phy-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c

+7 −2
Original line number Diff line number Diff line
@@ -590,6 +590,8 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll, 
	void __iomem *pll_base = rsc->pll_base;



	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FIVE_1, 0x01);

	MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00);

	MDSS_PLL_REG_W(pll_base, PLL_GEAR_BAND_SELECT_CONTROLS, 0x21);

	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FIVE, 0x01);

	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_TWO, 0x03);

	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_THREE, 0x00);
@@ -601,11 +603,15 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll, 
	MDSS_PLL_REG_W(pll_base, PLL_OUTDIV, 0x00);

	MDSS_PLL_REG_W(pll_base, PLL_CORE_OVERRIDE, 0x00);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_PROP_GAIN_RATE_1, 0x08);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_PROP_GAIN_RATE_1, 0x0a);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_BAND_SEL_RATE_1, 0xc0);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c);

	MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_OVERRIDE, 0x80);

	MDSS_PLL_REG_W(pll_base, PLL_PFILT, 0x29);

	MDSS_PLL_REG_W(pll_base, PLL_PFILT, 0x2f);

	MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x2a);

	MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x3f);

}
@@ -766,7 +772,6 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll, 
	MDSS_PLL_REG_W(pll_base, PLL_CMODE_1, 0x10);

	MDSS_PLL_REG_W(pll_base, PLL_CLOCK_INVERTERS_1,

			reg->pll_clock_inverters);



}



static int vco_7nm_set_rate(struct clk_hw *hw, unsigned long rate,

drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c

+2 −9
Original line number Diff line number Diff line
@@ -121,7 +121,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct dsi_phy_hw *phy, 
			    struct dsi_phy_cfg *cfg)

{

	int i;

	u8 tx_dctrl[] = {0x00, 0x00, 0x00, 0x00, 0x01};

	u8 tx_dctrl[] = {0x00, 0x00, 0x00, 0x04, 0x01};



	/* Strength ctrl settings */

	for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
@@ -143,9 +143,6 @@ static void dsi_phy_hw_v4_0_lane_settings(struct dsi_phy_hw *phy, 
		DSI_W32(phy, DSIPHY_LNX_TX_DCTRL(i), tx_dctrl[i]);

	}



	/* Toggle BIT 0 to release freeze I/0 */

	DSI_W32(phy, DSIPHY_LNX_TX_DCTRL(3), 0x05);

	DSI_W32(phy, DSIPHY_LNX_TX_DCTRL(3), 0x04);

}



/**
@@ -201,11 +198,7 @@ void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy, 


	/* Remove power down from all blocks */

	DSI_W32(phy, DSIPHY_CMN_CTRL_0, 0x7f);

	/*power up lanes */

	data = DSI_R32(phy, DSIPHY_CMN_CTRL_0);

	/* TODO: only power up lanes that are used */

	data |= 0x1F;

	DSI_W32(phy, DSIPHY_CMN_CTRL_0, data);



	DSI_W32(phy, DSIPHY_CMN_LANE_CTRL0, 0x1F);



	/* Select full-rate mode */