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Commit adcc4195 authored by Mukesh Ojha's avatar Mukesh Ojha
Browse files

ARM: dts: msm: Add cache-size property for Trinket 



Add d-cache-size/i-cache-size/cache-size property of respective
type caches to all the cpu nodes for Trinket, So that these
information could be accessed through sysfs
node.

Change-Id: I326363017f085bcff3e3f97f12052a328eb7fd04
Signed-off-by: default avatarMukesh Ojha <mojha@codeaurora.org>
parent 07ffd7cf

arch/arm64/boot/dts/qcom/trinket.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -56,11 +56,14 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x80000>;

			      cache-level = <2>;

			};

			L1_I_0: l1-icache {
@@ -85,6 +88,8 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;
@@ -111,6 +116,8 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;
@@ -137,6 +144,8 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;
@@ -163,11 +172,14 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1638>;

			sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;

			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x100000>;

			      cache-level = <2>;

			};
@@ -193,6 +205,8 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1638>;

			sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;

			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;
@@ -219,6 +233,8 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1638>;

			sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;

			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;
@@ -245,6 +261,8 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1638>;

			sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;

			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;