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Commit ac477afb authored by Jon Mason's avatar Jon Mason
Browse files

NTB: Enable 32bit Support 



Correct the issues on NTB that prevented it from working on x86_32 and
modify the Kconfig to allow it to be permitted to be used in that
environment as well.

Signed-off-by: default avatarJon Mason <jon.mason@intel.com>
parent be4dac0f

drivers/ntb/Kconfig

+1 −1
Original line number Original line Diff line number Diff line 
config NTB

config NTB

       tristate "Intel Non-Transparent Bridge support"

       tristate "Intel Non-Transparent Bridge support"

       depends on PCI

       depends on PCI

       depends on X86_64

       depends on X86

       help

       help

        The PCI-E Non-transparent bridge hardware is a point-to-point PCI-E bus

        The PCI-E Non-transparent bridge hardware is a point-to-point PCI-E bus

        connecting 2 systems.  When configured, writes to the device's PCI

        connecting 2 systems.  When configured, writes to the device's PCI

drivers/ntb/ntb_hw.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -376,7 +376,7 @@ void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw) 
 *

 *

 * RETURNS: the size of the memory window or zero on error

 * RETURNS: the size of the memory window or zero on error

 */

 */

resource_size_t ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw)

u64 ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw)

{

{

	if (mw >= ntb_max_mw(ndev))

	if (mw >= ntb_max_mw(ndev))

		return 0;

		return 0;
@@ -1257,7 +1257,7 @@ static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
		    ioremap_wc(pci_resource_start(pdev, MW_TO_BAR(i)),

		    ioremap_wc(pci_resource_start(pdev, MW_TO_BAR(i)),

			       ndev->mw[i].bar_sz);

			       ndev->mw[i].bar_sz);

		dev_info(&pdev->dev, "MW %d size %llu\n", i,

		dev_info(&pdev->dev, "MW %d size %llu\n", i,

			 pci_resource_len(pdev, MW_TO_BAR(i)));

			 (unsigned long long) ndev->mw[i].bar_sz);

		if (!ndev->mw[i].vbase) {

		if (!ndev->mw[i].vbase) {

			dev_warn(&pdev->dev, "Cannot remap BAR %d\n",

			dev_warn(&pdev->dev, "Cannot remap BAR %d\n",

				 MW_TO_BAR(i));

				 MW_TO_BAR(i));

drivers/ntb/ntb_hw.h

+16 −1
Original line number Original line Diff line number Diff line
@@ -62,6 +62,21 @@ 




#define msix_table_size(control)	((control & PCI_MSIX_FLAGS_QSIZE)+1)

#define msix_table_size(control)	((control & PCI_MSIX_FLAGS_QSIZE)+1)





#ifndef readq

static inline u64 readq(void __iomem *addr)

{

	return readl(addr) | (((u64) readl(addr + 4)) << 32LL);

}

#endif



#ifndef writeq

static inline void writeq(u64 val, void __iomem *addr)

{

	writel(val & 0xffffffff, addr);

	writel(val >> 32, addr + 4);

}

#endif



#define NTB_BAR_MMIO		0

#define NTB_BAR_MMIO		0

#define NTB_BAR_23		2

#define NTB_BAR_23		2

#define NTB_BAR_45		4

#define NTB_BAR_45		4
@@ -226,7 +241,7 @@ int ntb_read_local_spad(struct ntb_device *ndev, unsigned int idx, u32 *val); 
int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val);

int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val);

int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val);

int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val);

void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw);

void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw);

resource_size_t ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw);

u64 ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw);

void ntb_ring_sdb(struct ntb_device *ndev, unsigned int idx);

void ntb_ring_sdb(struct ntb_device *ndev, unsigned int idx);

void *ntb_find_transport(struct pci_dev *pdev);

void *ntb_find_transport(struct pci_dev *pdev);