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Commit ac2bf28a authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

Merge tag 'gvt-next-2018-06-19' of https://github.com/intel/gvt-linux into drm-intel-next-queued 



gvt-next-2018-06-19

- fine-grained per vgpu locking (Colin)
- fine-grained vgpu scheduler locking (Colin)
- deliver windows guest cursor hotspot info (Tina)
- GVT-g BXT support (Colin)
- other misc and checker fixes (Chris, Xinyun)

Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180619090043.ly6gquafbmxuus6h@zhen-hp.sh.intel.com
parents 1c3eced3 57c8a484

drivers/gpu/drm/i915/gvt/cmd_parser.c

+18 −25
Original line number Diff line number Diff line
@@ -172,6 +172,7 @@ struct decode_info { 
#define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)

#define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)

#define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)

#define OP_MEDIA_POOL_STATE                     OP_3D_MEDIA(0x2, 0x0, 0x5)



#define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)

#define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
@@ -1256,7 +1257,9 @@ static int gen8_check_mi_display_flip(struct parser_exec_state *s, 
	if (!info->async_flip)

		return 0;



	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) {

		stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);

		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &

				GENMASK(12, 10)) >> 10;
@@ -1284,7 +1287,9 @@ static int gen8_update_plane_mmio_from_mi_display_flip( 


	set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),

		      info->surf_val << 12);

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) {

		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),

			      info->stride_val);

		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
@@ -1308,7 +1313,9 @@ static int decode_mi_display_flip(struct parser_exec_state *s, 


	if (IS_BROADWELL(dev_priv))

		return gen8_decode_mi_display_flip(s, info);

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))

	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv))

		return skl_decode_mi_display_flip(s, info);



	return -ENODEV;
@@ -1317,26 +1324,14 @@ static int decode_mi_display_flip(struct parser_exec_state *s, 
static int check_mi_display_flip(struct parser_exec_state *s,

		struct mi_display_flip_command_info *info)

{

	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;



	if (IS_BROADWELL(dev_priv)

		|| IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv))

	return gen8_check_mi_display_flip(s, info);

	return -ENODEV;

}



static int update_plane_mmio_from_mi_display_flip(

		struct parser_exec_state *s,

		struct mi_display_flip_command_info *info)

{

	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;



	if (IS_BROADWELL(dev_priv)

		|| IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv))

	return gen8_update_plane_mmio_from_mi_display_flip(s, info);

	return -ENODEV;

}



static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
@@ -1615,15 +1610,10 @@ static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm, 
 */

static int batch_buffer_needs_scan(struct parser_exec_state *s)

{

	struct intel_gvt *gvt = s->vgpu->gvt;



	if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)

		|| IS_KABYLAKE(gvt->dev_priv)) {

		/* BDW decides privilege based on address space */

	/* Decide privilege based on address space */

	if (cmd_val(s, 0) & (1 << 8) &&

			!(s->vgpu->scan_nonprivbb & (1 << s->ring_id)))

		return 0;

	}

	return 1;

}
@@ -2349,6 +2339,9 @@ static struct cmd_info cmd_info[] = { 
	{"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,

		0, 16, NULL},



	{"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,

		0, 16, NULL},



	{"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},



	{"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/display.c

+42 −16
Original line number Diff line number Diff line
@@ -171,6 +171,29 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	int pipe;



	if (IS_BROXTON(dev_priv)) {

		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |

			BXT_DE_PORT_HP_DDIB |

			BXT_DE_PORT_HP_DDIC);



		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

				BXT_DE_PORT_HP_DDIA;

		}



		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

				BXT_DE_PORT_HP_DDIB;

		}



		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

				BXT_DE_PORT_HP_DDIC;

		}



		return;

	}



	vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |

			SDE_PORTC_HOTPLUG_CPT |

			SDE_PORTD_HOTPLUG_CPT);
@@ -337,26 +360,28 @@ void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt) 
	struct intel_gvt_irq *irq = &gvt->irq;

	struct intel_vgpu *vgpu;

	int pipe, id;

	int found = false;



	if (WARN_ON(!mutex_is_locked(&gvt->lock)))

		return;



	mutex_lock(&gvt->lock);

	for_each_active_vgpu(gvt, vgpu, id) {

		for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {

			if (pipe_is_enabled(vgpu, pipe))

				goto out;

			if (pipe_is_enabled(vgpu, pipe)) {

				found = true;

				break;

			}

		}

		if (found)

			break;

	}



	/* all the pipes are disabled */

	if (!found)

		hrtimer_cancel(&irq->vblank_timer.timer);

	return;



out:

	else

		hrtimer_start(&irq->vblank_timer.timer,

			ktime_add_ns(ktime_get(), irq->vblank_timer.period),

			HRTIMER_MODE_ABS);



	mutex_unlock(&gvt->lock);

}



static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
@@ -393,8 +418,10 @@ static void emulate_vblank(struct intel_vgpu *vgpu) 
{

	int pipe;



	mutex_lock(&vgpu->vgpu_lock);

	for_each_pipe(vgpu->gvt->dev_priv, pipe)

		emulate_vblank_on_pipe(vgpu, pipe);

	mutex_unlock(&vgpu->vgpu_lock);

}



/**
@@ -409,11 +436,10 @@ void intel_gvt_emulate_vblank(struct intel_gvt *gvt) 
	struct intel_vgpu *vgpu;

	int id;



	if (WARN_ON(!mutex_is_locked(&gvt->lock)))

		return;



	mutex_lock(&gvt->lock);

	for_each_active_vgpu(gvt, vgpu, id)

		emulate_vblank(vgpu);

	mutex_unlock(&gvt->lock);

}



/**

drivers/gpu/drm/i915/gvt/dmabuf.c

+19 −7
Original line number Diff line number Diff line
@@ -164,7 +164,9 @@ static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev, 


	obj->read_domains = I915_GEM_DOMAIN_GTT;

	obj->write_domain = 0;

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) {

		unsigned int tiling_mode = 0;

		unsigned int stride = 0;
@@ -192,6 +194,14 @@ static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev, 
	return obj;

}



static bool validate_hotspot(struct intel_vgpu_cursor_plane_format *c)

{

	if (c && c->x_hot <= c->width && c->y_hot <= c->height)

		return true;

	else

		return false;

}



static int vgpu_get_plane_info(struct drm_device *dev,

		struct intel_vgpu *vgpu,

		struct intel_vgpu_fb_info *info,
@@ -229,12 +239,14 @@ static int vgpu_get_plane_info(struct drm_device *dev, 
		info->x_pos = c.x_pos;

		info->y_pos = c.y_pos;



		/* The invalid cursor hotspot value is delivered to host

		 * until we find a way to get the cursor hotspot info of

		 * guest OS.

		 */

		if (validate_hotspot(&c)) {

			info->x_hot = c.x_hot;

			info->y_hot = c.y_hot;

		} else {

			info->x_hot = UINT_MAX;

			info->y_hot = UINT_MAX;

		}



		info->size = (((info->stride * c.height * c.bpp) / 8)

				+ (PAGE_SIZE - 1)) >> PAGE_SHIFT;

	} else {

drivers/gpu/drm/i915/gvt/edid.c

+19 −1
Original line number Diff line number Diff line
@@ -77,6 +77,20 @@ static unsigned char edid_get_byte(struct intel_vgpu *vgpu) 
	return chr;

}



static inline int bxt_get_port_from_gmbus0(u32 gmbus0)

{

	int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;

	int port = -EINVAL;



	if (port_select == 1)

		port = PORT_B;

	else if (port_select == 2)

		port = PORT_C;

	else if (port_select == 3)

		port = PORT_D;

	return port;

}



static inline int get_port_from_gmbus0(u32 gmbus0)

{

	int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
@@ -105,6 +119,7 @@ static void reset_gmbus_controller(struct intel_vgpu *vgpu) 
static int gmbus0_mmio_write(struct intel_vgpu *vgpu,

			unsigned int offset, void *p_data, unsigned int bytes)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	int port, pin_select;



	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
@@ -116,6 +131,9 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu, 
	if (pin_select == 0)

		return 0;



	if (IS_BROXTON(dev_priv))

		port = bxt_get_port_from_gmbus0(pin_select);

	else

		port = get_port_from_gmbus0(pin_select);

	if (WARN_ON(port < 0))

		return 0;

drivers/gpu/drm/i915/gvt/execlist.h

+5 −8
Original line number Diff line number Diff line
@@ -146,14 +146,11 @@ struct execlist_ring_context { 
	u32 nop4;

	u32 lri_cmd_2;

	struct execlist_mmio_pair ctx_timestamp;

	struct execlist_mmio_pair pdp3_UDW;

	struct execlist_mmio_pair pdp3_LDW;

	struct execlist_mmio_pair pdp2_UDW;

	struct execlist_mmio_pair pdp2_LDW;

	struct execlist_mmio_pair pdp1_UDW;

	struct execlist_mmio_pair pdp1_LDW;

	struct execlist_mmio_pair pdp0_UDW;

	struct execlist_mmio_pair pdp0_LDW;

	/*

	 * pdps[8]={ pdp3_UDW, pdp3_LDW, pdp2_UDW, pdp2_LDW,

	 *           pdp1_UDW, pdp1_LDW, pdp0_UDW, pdp0_LDW}

	 */

	struct execlist_mmio_pair pdps[8];

};



struct intel_vgpu_elsp_dwords {