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Commit ac1ad20f authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Will Deacon
Browse files

arm64: vhe: Verify CPU Exception Levels 



With a VHE capable CPU, kernel can run at EL2 and is a decided at early
boot. If some of the CPUs didn't start it EL2 or doesn't have VHE, we
could have CPUs running at different exception levels, all in the same
kernel! This patch adds an early check for the secondary CPUs to detect
such situations.

For each non-boot CPU add a sanity check to make sure we don't have
different run levels w.r.t the boot CPU. We save the information on
whether the boot CPU is running in hyp mode or not and ensure the
remaining CPUs match it.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
[will: made boot_cpu_hyp_mode static]
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 17eebd1a

arch/arm64/include/asm/virt.h

+6 −0
Original line number Original line Diff line number Diff line
@@ -60,6 +60,12 @@ static inline bool is_kernel_in_hyp_mode(void) 
	return el == CurrentEL_EL2;

	return el == CurrentEL_EL2;

}

}





#ifdef CONFIG_ARM64_VHE

extern void verify_cpu_run_el(void);

#else

static inline void verify_cpu_run_el(void) {}

#endif



/* The section containing the hypervisor text */

/* The section containing the hypervisor text */

extern char __hyp_text_start[];

extern char __hyp_text_start[];

extern char __hyp_text_end[];

extern char __hyp_text_end[];

arch/arm64/kernel/cpufeature.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -912,6 +912,7 @@ static u64 __raw_read_system_reg(u32 sys_id) 
 */

 */

static void check_early_cpu_features(void)

static void check_early_cpu_features(void)

{

{

	verify_cpu_run_el();

	verify_cpu_asid_bits();

	verify_cpu_asid_bits();

}

}

arch/arm64/kernel/smp.c

+38 −0
Original line number Original line Diff line number Diff line
@@ -75,6 +75,43 @@ enum ipi_msg_type { 
	IPI_WAKEUP

	IPI_WAKEUP

};

};





#ifdef CONFIG_ARM64_VHE



/* Whether the boot CPU is running in HYP mode or not*/

static bool boot_cpu_hyp_mode;



static inline void save_boot_cpu_run_el(void)

{

	boot_cpu_hyp_mode = is_kernel_in_hyp_mode();

}



static inline bool is_boot_cpu_in_hyp_mode(void)

{

	return boot_cpu_hyp_mode;

}



/*

 * Verify that a secondary CPU is running the kernel at the same

 * EL as that of the boot CPU.

 */

void verify_cpu_run_el(void)

{

	bool in_el2 = is_kernel_in_hyp_mode();

	bool boot_cpu_el2 = is_boot_cpu_in_hyp_mode();



	if (in_el2 ^ boot_cpu_el2) {

		pr_crit("CPU%d: mismatched Exception Level(EL%d) with boot CPU(EL%d)\n",

					smp_processor_id(),

					in_el2 ? 2 : 1,

					boot_cpu_el2 ? 2 : 1);

		cpu_panic_kernel();

	}

}



#else

static inline void save_boot_cpu_run_el(void) {}

#endif



#ifdef CONFIG_HOTPLUG_CPU

#ifdef CONFIG_HOTPLUG_CPU

static int op_cpu_kill(unsigned int cpu);

static int op_cpu_kill(unsigned int cpu);

#else

#else
@@ -401,6 +438,7 @@ void __init smp_cpus_done(unsigned int max_cpus) 
void __init smp_prepare_boot_cpu(void)

void __init smp_prepare_boot_cpu(void)

{

{

	cpuinfo_store_boot_cpu();

	cpuinfo_store_boot_cpu();

	save_boot_cpu_run_el();

	set_my_cpu_offset(per_cpu_offset(smp_processor_id()));

	set_my_cpu_offset(per_cpu_offset(smp_processor_id()));

}

}