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Commit aa3ae6de authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc 

Pull powerpc fixes from Ben Herrenschmidt:
 "Here are a few more fixes for powerpc 3.10.  It's a bit more than I
  would have liked this late in the game but I suppose that's what
  happens with a brand new chip generation coming out.

  A few regression fixes, some last minute fixes for new P8 features
  such as transactional memory,...

  There's also one powerpc KVM patch that I requested that adds two
  missing functions to our in-kernel interrupt controller support which
  is itself a new 3.10 feature.  These are defined by the base
  hypervisor specification.  We didn't implement them originally because
  Linux doesn't use them but they are simple and I'm not comfortable
  having a half-implemented interface in 3.10 and having to deal with
  versionning etc...  later when something starts needing those calls.
  They cannot be emulated in qemu when using in-kernel interrupt
  controller (not enough shared state).

  Just added a last minute patch to fix a typo introducing a breakage in
  our cputable for Power7+ processors, sorry about that, but the
  regression it fixes just hurt me :-)"

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
  powerpc/cputable: Fix typo on P7+ cputable entry
  powerpc/perf: Add missing SIER support
  powerpc/perf: Revert to original NO_SIPR logic
  powerpc/pci: Remove the unused variables in pci_process_bridge_OF_ranges
  powerpc/pci: Remove the stale comments of pci_process_bridge_OF_ranges
  powerpc/pseries: Always enable CONFIG_HOTPLUG_CPU on PSERIES SMP
  powerpc/kvm/book3s: Add support for H_IPOLL and H_XIRR_X in XICS emulation
  powerpc/32bit:Store temporary result in r0 instead of r8
  powerpc/mm: Always invalidate tlb on hpte invalidate and update
  powerpc/pseries: Improve stream generation comments in copypage/user
  powerpc/pseries: Kill all prefetch streams on context switch
  powerpc/cputable: Fix oprofile_cpu_type on power8
  powerpc/mpic: Fix irq distribution problem when MPIC_SINGLE_DEST_CPU
  powerpc/tm: Fix userspace stack corruption on signal delivery for active transactions
  powerpc/tm: Move TM abort cause codes to uapi
  powerpc/tm: Abort on emulation and alignment faults
  powerpc/tm: Update cause codes documentation
  powerpc/tm: Make room for hypervisor in abort cause codes
parents 008bd2de badec11b

Documentation/powerpc/transactional_memory.txt

+25 −2
Original line number Original line Diff line number Diff line
@@ -147,6 +147,25 @@ Example signal handler: 
      fix_the_problem(ucp->dar);

      fix_the_problem(ucp->dar);

    }

    }





When in an active transaction that takes a signal, we need to be careful with

the stack.  It's possible that the stack has moved back up after the tbegin.

The obvious case here is when the tbegin is called inside a function that

returns before a tend.  In this case, the stack is part of the checkpointed

transactional memory state.  If we write over this non transactionally or in

suspend, we are in trouble because if we get a tm abort, the program counter and

stack pointer will be back at the tbegin but our in memory stack won't be valid

anymore.



To avoid this, when taking a signal in an active transaction, we need to use

the stack pointer from the checkpointed state, rather than the speculated

state.  This ensures that the signal context (written tm suspended) will be

written below the stack required for the rollback.  The transaction is aborted

becuase of the treclaim, so any memory written between the tbegin and the

signal will be rolled back anyway.



For signals taken in non-TM or suspended mode, we use the

normal/non-checkpointed stack pointer.







Failure cause codes used by kernel

Failure cause codes used by kernel

==================================

==================================
@@ -155,14 +174,18 @@ These are defined in <asm/reg.h>, and distinguish different reasons why the 
kernel aborted a transaction:

kernel aborted a transaction:





 TM_CAUSE_RESCHED       Thread was rescheduled.

 TM_CAUSE_RESCHED       Thread was rescheduled.

 TM_CAUSE_TLBI          Software TLB invalide.

 TM_CAUSE_FAC_UNAV      FP/VEC/VSX unavailable trap.

 TM_CAUSE_FAC_UNAV      FP/VEC/VSX unavailable trap.

 TM_CAUSE_SYSCALL       Currently unused; future syscalls that must abort

 TM_CAUSE_SYSCALL       Currently unused; future syscalls that must abort

                        transactions for consistency will use this.

                        transactions for consistency will use this.

 TM_CAUSE_SIGNAL        Signal delivered.

 TM_CAUSE_SIGNAL        Signal delivered.

 TM_CAUSE_MISC          Currently unused.

 TM_CAUSE_MISC          Currently unused.

 TM_CAUSE_ALIGNMENT     Alignment fault.

 TM_CAUSE_EMULATE       Emulation that touched memory.





These can be checked by the user program's abort handler as TEXASR[0:7].

These can be checked by the user program's abort handler as TEXASR[0:7].  If



bit 7 is set, it indicates that the error is consider persistent.  For example

a TM_CAUSE_ALIGNMENT will be persistent while a TM_CAUSE_RESCHED will not.q





GDB

GDB

===

===

arch/powerpc/include/asm/hvcall.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -264,6 +264,7 @@ 
#define H_GET_MPP		0x2D4

#define H_GET_MPP		0x2D4

#define H_HOME_NODE_ASSOCIATIVITY 0x2EC

#define H_HOME_NODE_ASSOCIATIVITY 0x2EC

#define H_BEST_ENERGY		0x2F4

#define H_BEST_ENERGY		0x2F4

#define H_XIRR_X		0x2FC

#define H_RANDOM		0x300

#define H_RANDOM		0x300

#define H_COP			0x304

#define H_COP			0x304

#define H_GET_MPP_X		0x314

#define H_GET_MPP_X		0x314

arch/powerpc/include/asm/ppc_asm.h

+11 −0
Original line number Original line Diff line number Diff line
@@ -523,6 +523,17 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,946) 
#define PPC440EP_ERR42

#define PPC440EP_ERR42

#endif

#endif





/* The following stops all load and store data streams associated with stream

 * ID (ie. streams created explicitly).  The embedded and server mnemonics for

 * dcbt are different so we use machine "power4" here explicitly.

 */

#define DCBT_STOP_ALL_STREAM_IDS(scratch)	\

.machine push ;					\

.machine "power4" ;				\

       lis     scratch,0x60000000@h;		\

       dcbt    r0,scratch,0b01010;		\

.machine pop



/*

/*

 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them

 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them

 * keep the address intact to be compatible with code shared with

 * keep the address intact to be compatible with code shared with

arch/powerpc/include/asm/processor.h

+4 −9
Original line number Original line Diff line number Diff line
@@ -409,21 +409,16 @@ static inline void prefetchw(const void *x) 
#endif

#endif





#ifdef CONFIG_PPC64

#ifdef CONFIG_PPC64

static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)

static inline unsigned long get_clean_sp(unsigned long sp, int is_32)

{

{

	unsigned long sp;



	if (is_32)

	if (is_32)

		sp = regs->gpr[1] & 0x0ffffffffUL;

		return sp & 0x0ffffffffUL;

	else

		sp = regs->gpr[1];



	return sp;

	return sp;

}

}

#else

#else

static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)

static inline unsigned long get_clean_sp(unsigned long sp, int is_32)

{

{

	return regs->gpr[1];

	return sp;

}

}

#endif

#endif

arch/powerpc/include/asm/reg.h

+0 −11
Original line number Original line Diff line number Diff line
@@ -111,17 +111,6 @@ 
#define MSR_TM_TRANSACTIONAL(x)	(((x) & MSR_TS_MASK) == MSR_TS_T)

#define MSR_TM_TRANSACTIONAL(x)	(((x) & MSR_TS_MASK) == MSR_TS_T)

#define MSR_TM_SUSPENDED(x)	(((x) & MSR_TS_MASK) == MSR_TS_S)

#define MSR_TM_SUSPENDED(x)	(((x) & MSR_TS_MASK) == MSR_TS_S)





/* Reason codes describing kernel causes for transaction aborts.  By

   convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if

   the failure is persistent.

*/

#define TM_CAUSE_RESCHED	0xfe

#define TM_CAUSE_TLBI		0xfc

#define TM_CAUSE_FAC_UNAV	0xfa

#define TM_CAUSE_SYSCALL	0xf9 /* Persistent */

#define TM_CAUSE_MISC		0xf6

#define TM_CAUSE_SIGNAL		0xf4



#if defined(CONFIG_PPC_BOOK3S_64)

#if defined(CONFIG_PPC_BOOK3S_64)

#define MSR_64BIT	MSR_SF

#define MSR_64BIT	MSR_SF