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Commit a9e1aa1a authored by Aditya Bavanari's avatar Aditya Bavanari
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ARM: dts: msm: Add pmic id nodes for BCL support on sm6150 



Configuration of PMIC ID, SID and PPID is required for
BCL block to receive interrupts from PMIC. Add PMIC ID,
SID and PPID nodes to support BCL feature on WSA macro
and RX macro on sm6150 target.

CRs-Fixed: 2225097
Change-Id: I564d3a911ca33e0c92bcefc29ff97e41b0caaf12
Signed-off-by: default avatarAditya Bavanari <abavanar@codeaurora.org>
parent 4719c01d

Documentation/devicetree/bindings/sound/wcd_codec.txt

+8 −0
Original line number Diff line number Diff line
@@ -453,6 +453,9 @@ Required properties: 
 - clock-names : clock names defined for WSA macro

 - clocks : clock handles defined for WSA  macro

 - qcom,wsa-swr-gpios: phandle for SWR data and clock GPIOs of WSA macro

 - qcom,wsa-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order

			 required to be configured to receive interrupts

			 in BCL block of WSA macro



Example:
@@ -464,6 +467,7 @@ Example: 
		clocks = <&clock_audio_wsa_1 0>,

		<&clock_audio_wsa_2 0>;

		qcom,wsa-swr-gpios = &wsa_swr_gpios;

		qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;

	};

};
@@ -497,6 +501,9 @@ Required properties: 
 - clocks : clock handles defined for RX macro

 - qcom,rx-swr-gpios: phandle for SWR data and clock GPIOs of RX macro

 - qcom,rx_mclk_mode_muxsel: register address for RX macro MCLK mode mux select

 - qcom,rx-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order

			 required to be configured to receive interrupts

			 in BCL block of WSA macro



Example:
@@ -509,6 +516,7 @@ Example: 
			 <&clock_audio_rx_2 0>;

		qcom,rx-swr-gpios = <&rx_swr_gpios>;

		qcom,rx_mclk_mode_muxsel = <0x62C25020>;

		qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;

		swr_1: rx_swr_master {

			compatible = "qcom,swr-mstr";

			wcd937x_rx_slave: wcd937x-rx-slave {

arch/arm64/boot/dts/qcom/sm6150-audio-overlay.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ 
			 <&clock_audio_rx_2 0>;

		qcom,rx-swr-gpios = <&rx_swr_gpios>;

		qcom,rx_mclk_mode_muxsel = <0x62c25020>;

		qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;

		swr1: rx_swr_master {

			compatible = "qcom,swr-mstr";

			#address-cells = <2>;
@@ -90,6 +91,7 @@ 
		clocks = <&clock_audio_wsa_1 0>,

			 <&clock_audio_wsa_2 0>;

		qcom,wsa-swr-gpios = <&wsa_swr_gpios>;

		qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;

		swr0: wsa_swr_master {

			compatible = "qcom,swr-mstr";

			#address-cells = <2>;