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Commit a91b2e69 authored by Ritesh Harjani's avatar Ritesh Harjani Committed by Andy Gross
Browse files

ARM: dts: Add xo to sdhc clock node on qcom platforms 



Add xo entry to sdhc clock node on all qcom platforms.

Signed-off-by: default avatarRitesh Harjani <riteshh@codeaurora.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent d4714a5a

arch/arm/boot/dts/qcom-apq8084.dtsi

+10 −6
Original line number Diff line number Diff line
@@ -182,13 +182,13 @@ 
	};



	clocks {

		xo_board {

		xo_board: xo_board {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <19200000>;

		};



		sleep_clk {

		sleep_clk: sleep_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <32768>;
@@ -416,8 +416,10 @@ 
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 123 0>, <0 138 0>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;

			clock-names = "core", "iface";

			clocks = <&gcc GCC_SDCC1_APPS_CLK>,

				 <&gcc GCC_SDCC1_AHB_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			status = "disabled";

		};
@@ -427,8 +429,10 @@ 
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 125 0>, <0 221 0>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;

			clock-names = "core", "iface";

			clocks = <&gcc GCC_SDCC2_APPS_CLK>,

				 <&gcc GCC_SDCC2_AHB_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			status = "disabled";

		};

arch/arm/boot/dts/qcom-msm8974.dtsi

+10 −6
Original line number Diff line number Diff line
@@ -220,13 +220,13 @@ 
	};



	clocks {

		xo_board {

		xo_board: xo_board {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <19200000>;

		};



		sleep_clk {

		sleep_clk: sleep_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <32768>;
@@ -558,8 +558,10 @@ 
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 123 0>, <0 138 0>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;

			clock-names = "core", "iface";

			clocks = <&gcc GCC_SDCC1_APPS_CLK>,

				 <&gcc GCC_SDCC1_AHB_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			status = "disabled";

		};
@@ -569,8 +571,10 @@ 
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 125 0>, <0 221 0>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;

			clock-names = "core", "iface";

			clocks = <&gcc GCC_SDCC2_APPS_CLK>,

				 <&gcc GCC_SDCC2_AHB_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			status = "disabled";

		};