Commit a8e45a1c authored Jul 17, 2017 by Navare, Manasi D Committed by Daniel Vetter Jul 27, 2017

drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence



The condition for setting the Loadgen Select bit of
PORT_TX_DW4 register during DDI Vswing Sequence should be
Bit rate <=6 GHz whereas the existing code checks only
Bit Rate < 6GHz. This patch fixes this condition.
While at it also remove the redundant paranthesis.

Fixes: cf54ca8b ("drm/i915/cnl: Implement voltage swing sequence.")
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1500329122-32662-1-git-send-email-manasi.d.navare@intel.com


Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent 525a4f93

drivers/gpu/drm/i915/intel_ddi.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -2013,8 +2013,8 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
	val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
	val &= ~LOADGEN_SELECT;		val &= ~LOADGEN_SELECT;

	if (((rate < 600000) && (width == 4) && (ln >= 1)) \|\|		if ((rate <= 600000 && width == 4 && ln >= 1) \|\|
	((rate < 600000) && (width < 4) && ((ln == 1) \|\| (ln == 2)))) {		(rate <= 600000 && width < 4 && (ln == 1 \|\| ln == 2))) {
	val \|= LOADGEN_SELECT;		val \|= LOADGEN_SELECT;
	}		}
	I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);