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Commit a575a973 authored by Shefali Jain's avatar Shefali Jain
Browse files

clk: qcom: Update RCG div of dp_phy_pll_link_clk for SDMMMAGPIE 



As per clock frequency plan update the RCG div of
dp_phy_pll_link_clk to get correct the frequencies.

Change-Id: I520dd0d0e7163b37d095bfa4fea03ee69cbe8e0e
Signed-off-by: default avatarShefali Jain <shefjain@codeaurora.org>
parent 3424e1d3

drivers/clk/qcom/dispcc-sdmmagpie.c

+2 −2
Original line number Diff line number Diff line
@@ -300,8 +300,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { 
};



static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = {

	F(162000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0),

	F(270000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0),

	F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),

	F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),

	F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),

	F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),

	{ }