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Commit a521ee98 authored by Vasanthakumar Thiagarajan's avatar Vasanthakumar Thiagarajan Committed by Kalle Valo
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ath10k: Add new reg_address/mask to hw register table 



Add more register address and mask which can be different
for newer chip to hw_reg table.

Signed-off-by: default avatarVasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
parent 2f2cfc4a

drivers/net/wireless/ath/ath10k/ce.h

+4 −2
Original line number Original line Diff line number Diff line
@@ -423,8 +423,10 @@ static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id) 




#define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))

#define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))





#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB		8

#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \

#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK		0x0000ff00

				ar->regs->ce_wrap_intr_sum_host_msi_lsb

#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \

				ar->regs->ce_wrap_intr_sum_host_msi_mask

#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \

#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \

	(((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \

	(((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \

		CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)

		CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)

drivers/net/wireless/ath/ath10k/hw.c

+18 −4
Original line number Original line Diff line number Diff line
@@ -34,8 +34,15 @@ const struct ath10k_hw_regs qca988x_regs = { 
	.ce7_base_address		= 0x00059000,

	.ce7_base_address		= 0x00059000,

	.soc_reset_control_si0_rst_mask	= 0x00000001,

	.soc_reset_control_si0_rst_mask	= 0x00000001,

	.soc_reset_control_ce_rst_mask	= 0x00040000,

	.soc_reset_control_ce_rst_mask	= 0x00040000,

	.soc_chip_id_address		= 0x00ec,

	.soc_chip_id_address		= 0x000000ec,

	.scratch_3_address		= 0x0030,

	.scratch_3_address		= 0x00000030,

	.fw_indicator_address		= 0x00009030,

	.pcie_local_base_address	= 0x00080000,

	.ce_wrap_intr_sum_host_msi_lsb	= 0x00000008,

	.ce_wrap_intr_sum_host_msi_mask	= 0x0000ff00,

	.pcie_intr_fw_mask		= 0x00000400,

	.pcie_intr_ce_mask_all		= 0x0007f800,

	.pcie_intr_clr_address		= 0x00000014,

};

};





const struct ath10k_hw_regs qca6174_regs = {

const struct ath10k_hw_regs qca6174_regs = {
@@ -54,8 +61,15 @@ const struct ath10k_hw_regs qca6174_regs = { 
	.ce7_base_address			= 0x00036000,

	.ce7_base_address			= 0x00036000,

	.soc_reset_control_si0_rst_mask		= 0x00000000,

	.soc_reset_control_si0_rst_mask		= 0x00000000,

	.soc_reset_control_ce_rst_mask		= 0x00000001,

	.soc_reset_control_ce_rst_mask		= 0x00000001,

	.soc_chip_id_address			= 0x000f0,

	.soc_chip_id_address			= 0x000000f0,

	.scratch_3_address			= 0x0028,

	.scratch_3_address			= 0x00000028,

	.fw_indicator_address			= 0x00009028,

	.pcie_local_base_address		= 0x00080000,

	.ce_wrap_intr_sum_host_msi_lsb		= 0x00000008,

	.ce_wrap_intr_sum_host_msi_mask		= 0x0000ff00,

	.pcie_intr_fw_mask			= 0x00000400,

	.pcie_intr_ce_mask_all			= 0x0007f800,

	.pcie_intr_clr_address			= 0x00000014,

};

};





const struct ath10k_hw_values qca988x_values = {

const struct ath10k_hw_values qca988x_values = {

drivers/net/wireless/ath/ath10k/hw.h

+12 −5
Original line number Original line Diff line number Diff line
@@ -164,6 +164,13 @@ struct ath10k_hw_regs { 
	u32 soc_reset_control_ce_rst_mask;

	u32 soc_reset_control_ce_rst_mask;

	u32 soc_chip_id_address;

	u32 soc_chip_id_address;

	u32 scratch_3_address;

	u32 scratch_3_address;

	u32 fw_indicator_address;

	u32 pcie_local_base_address;

	u32 ce_wrap_intr_sum_host_msi_lsb;

	u32 ce_wrap_intr_sum_host_msi_mask;

	u32 pcie_intr_fw_mask;

	u32 pcie_intr_ce_mask_all;

	u32 pcie_intr_clr_address;

};

};





extern const struct ath10k_hw_regs qca988x_regs;

extern const struct ath10k_hw_regs qca988x_regs;
@@ -386,7 +393,7 @@ enum ath10k_hw_rate_cck { 
#define CE7_BASE_ADDRESS			ar->regs->ce7_base_address

#define CE7_BASE_ADDRESS			ar->regs->ce7_base_address

#define DBI_BASE_ADDRESS			0x00060000

#define DBI_BASE_ADDRESS			0x00060000

#define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS	0x0006c000

#define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS	0x0006c000

#define PCIE_LOCAL_BASE_ADDRESS			0x00080000

#define PCIE_LOCAL_BASE_ADDRESS		ar->regs->pcie_local_base_address





#define SOC_RESET_CONTROL_ADDRESS		0x00000000

#define SOC_RESET_CONTROL_ADDRESS		0x00000000

#define SOC_RESET_CONTROL_OFFSET		0x00000000

#define SOC_RESET_CONTROL_OFFSET		0x00000000
@@ -460,7 +467,7 @@ enum ath10k_hw_rate_cck { 
#define CORE_CTRL_ADDRESS			0x0000

#define CORE_CTRL_ADDRESS			0x0000

#define PCIE_INTR_ENABLE_ADDRESS		0x0008

#define PCIE_INTR_ENABLE_ADDRESS		0x0008

#define PCIE_INTR_CAUSE_ADDRESS			0x000c

#define PCIE_INTR_CAUSE_ADDRESS			0x000c

#define PCIE_INTR_CLR_ADDRESS			0x0014

#define PCIE_INTR_CLR_ADDRESS			ar->regs->pcie_intr_clr_address

#define SCRATCH_3_ADDRESS			ar->regs->scratch_3_address

#define SCRATCH_3_ADDRESS			ar->regs->scratch_3_address

#define CPU_INTR_ADDRESS			0x0010

#define CPU_INTR_ADDRESS			0x0010
@@ -468,13 +475,13 @@ enum ath10k_hw_rate_cck { 
#define CCNT_TO_MSEC(x) ((x) / 88000)

#define CCNT_TO_MSEC(x) ((x) / 88000)





/* Firmware indications to the Host via SCRATCH_3 register. */

/* Firmware indications to the Host via SCRATCH_3 register. */

#define FW_INDICATOR_ADDRESS	(SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS)

#define FW_INDICATOR_ADDRESS			ar->regs->fw_indicator_address

#define FW_IND_EVENT_PENDING			1

#define FW_IND_EVENT_PENDING			1

#define FW_IND_INITIALIZED			2

#define FW_IND_INITIALIZED			2





/* HOST_REG interrupt from firmware */

/* HOST_REG interrupt from firmware */

#define PCIE_INTR_FIRMWARE_MASK			0x00000400

#define PCIE_INTR_FIRMWARE_MASK			ar->regs->pcie_intr_fw_mask

#define PCIE_INTR_CE_MASK_ALL			0x0007f800

#define PCIE_INTR_CE_MASK_ALL			ar->regs->pcie_intr_ce_mask_all





#define DRAM_BASE_ADDRESS			0x00400000

#define DRAM_BASE_ADDRESS			0x00400000